參數(shù)資料
型號： MPC7410VS500LE
廠商： Freescale Semiconductor
文件頁數(shù)： 6/56頁
文件大小： 0K
描述： IC MPU PPC 500MHZ 360-FCCLGA
標準包裝： 44
系列： MPC74xx
處理器類型： 32-位 MPC74xx PowerPC
速度： 500MHz
電壓： 1.8V
安裝類型： 表面貼裝
封裝/外殼： 360-CLGA，F(xiàn)CCLGA
供應商設備封裝： 360-FCCLGA（25x25）
包裝： 托盤
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
14
Freescale Semiconductor
Electrical and Thermal Characteristics
4.2.1
Clock AC Specifications
Table 7 provides the clock AC timing specifications as defined in Figure 3.
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
Table 7. Clock AC Timing Specifications
At recommended operating conditions (see Table 3)
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
400 MHz
450 MHz
500 MHz
Min
Max
Min
Max
Min
Max
Processor frequency
fcore
350
400
350
450
350
500
MHz
1
VCO frequency
fVCO
700
800
700
900
700
1000
MHz
1
SYSCLK frequency
fSYSCLK
33
133
33
133
33
133
MHz
1
SYSCLK cycle time
tSYSCLK
7.5
30
7.5
30
7.5
30
ns
—
SYSCLK rise and fall time
tKR and tKF
—
0.5
—
0.5
—
0.5
ns/V
2
SYSCLK duty cycle
measured at OVDD/2
tKHKL/tSYSCLK
40
60
40
60
40
60
%
3
SYSCLK jitter
—
±150
—
±150
—
±150
ps
4
Internal PLL-relock time
—
100
—
100
—
100
μs5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:3] signal description in Section 8.1, “PLL Configuration,” for valid PLL_CFG[0:3]
settings.
2. Rise and fall times measurement are determined by the slew rates of the bus interface, rather than by time. As a result, the
0.5 ns rise/fall time spec of the 1.8- and 2.5-V bus interfaces is equivalent to the 1 ns rise/fall time of the 3.3-V bus interface.
Both interfaces required a 2 V/ns slew rate. The slew rate is measured as a 1-V change (from 0.2 to 1.2 V) in 0.5 ns for the
1.8- and 2.5-V bus interfaces, whereas the 3.3-V bus interface required a 2-V change (from 0.4 to 2.4 V) in 1 ns.
3. Timing is guaranteed by design and characterization.
4. This represents total input jitter—short- and long-term combined—and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL
lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when
the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted
for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
SYSCLK
VM
CVIH
CVIL
VM = Midpoint Voltage (OVDD/2)
tSYSCLK
tKR
tKF
tKHKL
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