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參數(shù)資料
| 型號： | MPC7410VS500LE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 55/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PPC 500MHZ 360-FCCLGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 500MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CLGA，F(xiàn)CCLGA |
| 供應(yīng)商設(shè)備封裝： | 360-FCCLGA（25x25） |
| 包裝： | 托盤 |
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MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
8
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 2 shows the allowable undershoot and overshoot voltage for the MPC7410.
Figure 2. Overshoot/Undershoot Voltage
The MPC7410 provides several I/O voltages to support both compatibility with existing systems and migration to
future systems. The MPC7410 core voltage must always be provided at nominal voltage (see Table 3 for actual
recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are provided through separate sets
of supply pins and may be provided at the voltages shown in Table 2. Voltage must be provided to the L2OVDD
power pins even if the interface is not used. The input voltage threshold for each bus is selected by sampling the
state of the voltage select pins BVSEL and L2VSEL at the negation of the signal HRESET. These signals must
remain stable during part operation and cannot change. The output voltage will swing from GND to the maximum
voltage applied to the OVDD or L2OVDD power pins.
Rework temperature
Trwk
260
°C
—
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only,
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
2. Caution: Vin must not exceed OVDD or L2OVDD by more than 0.2 V at any time including during power-on reset.
3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 2.0 V at any time including during
power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down
sequences.
4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4 V at any time including during
power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down
sequences.
6. M
xx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OVDD and have a maximum
value OVDD of –0.3 to 2.8 V.
Table 1. Absolute Maximum Ratings 1 (continued)
Characteristic
Symbol
Maximum Value
Unit
Notes
VIH
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
(L2)OVDD + 20%
VIL
(L2)OVDD
(L2)OVDD + 5%
of tSYSCLK (OVDD)
or tL2CLK (L2OVDD)
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