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參數(shù)資料
| 型號： | MPC5534MVM80 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 54/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 1MB FLASH 80MHZ 208MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | MPC55xx Qorivva |
| 核心處理器： | e200z6 |
| 芯體尺寸： | 32-位 |
| 速度： | 80MHz |
| 連通性： | CAN，EBI/EMI，以太網(wǎng)，SCI，SPI |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 192 |
| 程序存儲器容量： | 1MB（1M x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.35 V ~ 1.65 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 34x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 208-BGA |
| 包裝： | 托盤 |
| 其它名稱： | Q4437099 T0850514 |
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MPC5534 Microcontroller Data Sheet, Rev. 6
Revision History for the MPC5534 Data Sheet
Freescale Semiconductor
58
Table 25, eMIOS Timing:
Deleted (MTS) from the heading, table, and footnotes.
Footnote 1: Changed ‘VDDEH = 3.0–5.5;’ to ‘VDDEH = 3.0–5.25;’
Footnote 1: Deleted ‘FSYS = 80 MHz,’ ‘VDD = 1.35–1.65 V’, ‘VDD33 and VDDSYN = 3.0–3.6 V’ and
‘a(chǎn)nd CL = 200 pF with SRC = 0b11.’
Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
Figure 17, eMIOS Timing: Added figure.
Table 26, DSPI Timing:
Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max speed is the maximum
speed allowed including frequency modulation (FM). 42 MHz parts allow for 40 MHz system clock + 2% FM;
68 MHz parts allow for 66 MHz system clock + 2% FM, and 82 MHz parts allow for 80 MHz system clock + 2% FM.
Spec1:SCK Cycle Time: changes to values: 40 MHz, min. = 48.8 ns, max = 5.8 ms; 66 MHz, min. = 28.4 ns,
max = 3.5 ms; 80 MHz min. = 24.4 ns, max = 2.9 ms.
Spec 2: PCS to SCK delay: 40 MHz, min. = 46 ns; 66 MHz, min. = 26 ns; 80 MHz min. = 22 ns.
Spec 3: After SCK delay: 40 MHz, min. = 45 ns; 66 MHz, min. = 25 ns; 80 MHz min. = 21 ns.
Spec 9: Data setup time for inputs, Master (MTFE = 1, CPHA = 0): 66 MHz, min. = 6 ns; 80 MHz min. = 8 ns.
Spec 10: Data hold time for inputs, Master (MTFE = 1, CPHA = 0): 40 MHz, min. = 45 ns; 66 MHz, min. = 25 ns;
80 MHz min. = 21 ns.
Spec 11: Data valid (after SCK edge), Master (MTFE = 1, CPHA = 0): 40 MHz, max. = 45 ns;
66 MHz, max. = 25 ns; 80 MHz max. = 21 ns.
Footnote 1: Changed ‘VDDEH = 3.0–5.5;’ to ‘VDDEH = 3.0–5.25;’
Footnote 1: Added to beginning of footnote 1 ‘All DSPI timing specifications use the fastest slew rate (SRC =
0b11) on pad type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew
rate.’
Footnote 1: Deleted ‘VDD = 1.35–1.65 V’ and ‘VDD33 and VDDSYN = 3.0–3.6 V.
Table 27, EQADC SSI Timing Characteristics:
Footnote 1: Changed ‘VDDEH = 3.0–5.5;’ to ‘VDDEH = 3.0–5.25;’
Deleted from table title ‘(Pads at 3.3 V or 5.0 V)’
Deleted 1st line in table ‘CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.’
Spec 1: FCK frequency -- removed.
Combined footnotes 1 and 2, and moved the new footnote to Spec 2. Moved old footnote 3 that is now
footnote 2 to Spec 2.
Footnote 1, deleted ‘VDD = 1.35–1.65 V’ and ‘VDD33 and VDDSYN = 3.0–3.6V.’
Changed ‘CL = 50 pF’ to ‘CL = 25 pF.’
Footnote 2: added ‘cycle’ after ‘duty’ to read: FCK duty cycle is not 50% when . . . .
Figure 28, MPC5534 208 Package and Figure 29 MPC5534 324 Package: Deleted the version number and date.
Figure 30, MPC5534 208 Package Dimensions and Figure 31 MPC5534 324 Package Dimensions:
Deleted the version number and date.
Table 30. Table and Figure Changes Between Rev. 3.0 and 4.0 (continued)
Location
Description of Changes
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