參數(shù)資料
型號(hào)： MPC5534MVM80
廠商： Freescale Semiconductor
文件頁數(shù)： 49/60頁
文件大小： 0K
描述： MCU 1MB FLASH 80MHZ 208MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： MPC55xx Qorivva
核心處理器： e200z6
芯體尺寸： 32-位
速度： 80MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，SCI，SPI
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 192
程序存儲(chǔ)器容量： 1MB（1M x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.35 V ~ 1.65 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 34x12b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 208-BGA
包裝： 托盤
其它名稱： Q4437099
T0850514
Revision History for the MPC5534 Data Sheet
MPC5534 Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
53
5.3
Changes Between Revisions 3.0 and 4.0
The following table lists the substantive text changes made to paragraphs.
Last paragraph: Changed the first sentence FROM . . . the voltage on the pins goes to high-impedance until . . .
TO. . .the pins go to a high-impedance state until . . .
Table 29. Text Changes Between Rev. 3.0 and 4.0
Location
Description of Changes
Title Page:
Changed the Revision number from 3.0 to 4.0. Changed the date format to DD MMM YYYY. Made the same
changes in the lower left corner of the back page.
Added the sentence directly preceding Table 1: ‘Unless noted in this data sheet, all specifications apply
from TL to TH.’
Sections 3.7.1, 3.7.2 and 3.7.3: Reordered sections resulting in the following order and section renumbering:
Added the following text directly before this section and after Table 8 Pin Status for Medium and Slow Pads During
the Power-on Sequence:
‘The values in Table 7 and Table 8 do not include the effect of the weak pull devices on the output pins during
power up.
Before exiting the internal POR state, the voltage on the pins goes to high-impedance until POR negates. When
the internal POR negates, the functional state of the signal during reset applies and the weak pull devices (up
or down) are enabled as defined in the device Reference Manual. If VDD is too low to correctly propagate the
logic signals, the weak-pull devices can pull the signals to VDDE and VDDEH.
To avoid this condition, minimize the ramp time of the VDD supply to a time period less than the time required to
enable the external circuitry connected to the device outputs.’
Section 3.7.3, “Power-Down Sequence (VRC33 Grounded)” Deleted the underscore in ORed_POR to become ORed POR.
Table 28. Text Changes Between Rev. 4.0 and 5.0 (continued)
Location
Description of Changes
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