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參數(shù)資料
型號(hào)： MPC5534MVM80
廠商： Freescale Semiconductor
文件頁數(shù)： 35/60頁
文件大?。?/td> 0K
描述： MCU 1MB FLASH 80MHZ 208MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： MPC55xx Qorivva
核心處理器： e200z6
芯體尺寸： 32-位
速度： 80MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，SCI，SPI
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 192
程序存儲(chǔ)器容量： 1MB（1M x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.35 V ~ 1.65 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 34x12b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 208-BGA
包裝： 托盤
其它名稱： Q4437099
T0850514
MPC5534 Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
40
8PCSS to PCSx time
tPASC
5
—5
—
5
—ns
9
Data setup time for inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
tSUI
20
2
–4
20
—
20
2
6
20
—
20
2
8
20
—
ns
10
Data hold time for inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)7
Master (MTFE = 1, CPHA = 1)
tHI
–4
7
45
–4
—
–4
7
25
–4
—
–4
7
21
–4
—
ns
11
Data valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tSUO
—
5
25
45
5
—
5
25
5
—
5
25
21
5
ns
12
Data hold time for outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tHO
–5
5.5
8
–5
—
–5
5.5
4
–5
—
–5
5.5
3
–5
—
ns
1 All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of
S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0–5.25 V, TA = TL to TH, and
CL = 50 pF with SRC = 0b11.
2
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).
42 MHz parts allow for 40 MHz system clock + 2% FM; 68 MHz parts allow for a 66 MHz system clock + 2% FM, and
82 MHz parts allow for 80 MHz system clock + 2% FM.
3 The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.
These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.
4 The actual minimum SCK cycle time is limited by pad performance.
5 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
6 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
7 This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10.
Table 26. DSPI Timing 1, 2 (continued)
Spec
Characteristic
Symbol
40 MHz
66 MHz
80 MHz
Unit
Min.
Max
Min.
Max
Min.
Max
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