參數(shù)資料
型號： MPC5534MVM80
廠商： Freescale Semiconductor
文件頁數(shù)： 52/60頁
文件大?。?/td> 0K
描述： MCU 1MB FLASH 80MHZ 208MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： MPC55xx Qorivva
核心處理器： e200z6
芯體尺寸： 32-位
速度： 80MHz
連通性： CAN，EBI/EMI，以太網(wǎng)，SCI，SPI
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 192
程序存儲器容量： 1MB（1M x 8）
程序存儲器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.35 V ~ 1.65 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 34x12b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 208-BGA
包裝： 托盤
其它名稱： Q4437099
T0850514
MPC5534 Microcontroller Data Sheet, Rev. 6
Revision History for the MPC5534 Data Sheet
Freescale Semiconductor
56
Table 12, FMPLL Electrical Characteristics:
Spec 1, footnote 1 in column 2: ‘PLL reference frequency range’: Added that reads ‘Nominal crystal and external
reference values are worst-case not more than 1%. The device operates correctly if the frequency remains within
± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.‘
Spec 1, footnote 2 in column 1: Changed to: ‘The 8–20 MHz crystal or external reference values have PLLCFG[2]
pulled low’ and applies to spec 1, column 2, crystal reference and external reference.
Spec 21, column 2: Changed fref_crystal to fref in ICO frequency equation, and
added the same equation but substituted fref_ext for fref for the external reference clock, giving:
fico = [ fref_crystal (MFD + 4) ] (PREDIV + 1)
fico = [ fref_ext (MFD + 4) ] (PREDIV + 1)
Spec 21: Changed column 5 from ‘fSYS’ MHz’ to: ‘fMAX’.
Spec 22: Changed column 4, Max Value from fMAX to 20, and added footnote 17 to read, ‘Maximum value for
dual controller (1:1) mode is (fMAX 2) and the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).’
Table 13, eQADC Conversion Specifications: Changed ‘(Operating)’ to ‘(TA = TL – TH)’ to the table title.
Table 14, Flash Program and Erase Specifications:
Added (TA = TL – TH) to the table title.
Spec 8, 128 KB block pre-program and erase time, Max column value from 15,000 to 7,500.
Moved footnote 1 from the table title to directly after the ‘Typical’ in the column 5 header.
Footnote 2: Changed from: ‘Initial factory condition:
100program/erase cycles, 25 oC, typical supply voltage,
80 MHz minimum system frequency.‘ To: ‘Initial factory condition:
100program/erase cycles, 25 oC, using a
typical supply voltage measured at a minimum system frequency of 80 MHz.’
Table 15, Flash EEPROM Module Life:
Replaced (Full Temperature Range) with (TA = TL – TH) in the table title.
Spec 1b, Min. column value changed from 10,000 to 1,000.
Table 16, FLash BIU Settings vs. Frequency of Operations:
‘Added footnote 1 to the end of the table title, The footnote reads: ‘Illegal combinations exist. Use entries from
the same row in this table.’
Moved footnote 2:’ For maximum flash performance, set to 0b11’ to the ‘DPFEN’ column header.
Deleted the x-refs in the ‘DPFEN’ column for the rows.
Created a x-ref for footnote 2 and inserted in the ‘IPFEN’ column header.
Deleted the x-refs in the ‘IPFEN’ column for the rows.
Added to the PFLIM binary values a leading 0 so that 0bxx became 0b0xx.
Moved footnote 3:’ For maximum flash performance, set to 0b110’ to the ‘PFLIM’ column header.
Deleted the x-refs in the ‘PFLIM’ column for the rows.
Moved footnote 4:’ For maximum flash performance, set to 0b1’ to the ‘BFEN’ column header.
Deleted the x-refs in the ‘BFEN’ column for the rows.
Added footnotes 4, 6, 7, and 8:
-- footnote 4
27 MHz parts allow for 25 MHz system clock + 2% frequency modulation (FM).
-- footnote 5
52 MHz parts allow for 50 MHz system clock + 2% FM.
-- footnote 6
77 MHz parts allow for 75 MHz system clock + 2% FM.
-- footnote 7
82 MHz parts allow for 80 MHz system clock + 2% FM.
Table 30. Table and Figure Changes Between Rev. 3.0 and 4.0 (continued)
Location
Description of Changes
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