MOTOROLA
3-12
CENTRAL PROCESSING UNIT
Rev. 15 June 98
MPC509
USER’S MANUAL
Table 3-3 FPSCR Bit Settings
Bit(s)
Name
Description
0
FX
Floating-point exception summary. Every floating-point instruction implicitly sets FPSCR[FX] if
that instruction causes any of the floating-point exception bits in the FPSCR to change from zero
to one. The
mcrfs
instruction implicitly clears FPSCR[FX] if the FPSCR field containing
FPSCR[FX] is copied. The
mtfsf
,
mtfsfi
,
mtfsb0
, and
mtfsb1
instructions can set or clear
FPSCR[FX] explicitly. This is a sticky bit.
Floating-point enabled exception summary. This bit signals the occurrence of any of the enabled
exception conditions. It is the logical OR of all the floating-point exception bits masked with their
respective enable bits. The
mcrfs
instruction implicitly clears FPSCR[FEX] if the result of the log-
ical OR described above becomes zero. The
mtfsf
,
mtfsfi
,
mtfsb0
, and
mtfsb1
instructions
cannot set or clear FPSCR[FEX] explicitly. This is not a sticky bit.
Floating-point invalid operation exception summary. This bit signals the occurrence of any invalid
operation exception. It is the logical OR of all of the invalid operation exceptions. The
mcrfs
instruction implicitly clears FPSCR[VX] if the result of the logical OR described above becomes
zero. The
mtfsf
,
mtfsfi
,
mtfsb0
, and
mtfsb1
instructions cannot set or clear FPSCR[VX] explic-
itly. This is not a sticky bit.
Floating-point overflow exception. This is a sticky bit.
Floating-point underflow exception. This is a sticky bit.
Floating-point zero divide exception. This is a sticky bit.
Floating-point inexact exception. This is a sticky bit.
Floating-point invalid operation exception for SNaN. This is a sticky bit.
Floating-point invalid operation exception for ×-×. This is a sticky bit.
Floating-point invalid operation exception for ×/×. This is a sticky bit.
Floating-point invalid operation exception for 0/0. This is a sticky bit.
Floating-point invalid operation exception for ×*0. This is a sticky bit.
Floating-point invalid operation exception for invalid compare. This is a sticky bit.
Floating-point fraction rounded. The last floating-point instruction that potentially rounded the
intermediate result incremented the fraction. This bit is not sticky.
Floating-point fraction inexact. The last floating-point instruction that potentially rounded the
intermediate result produced an inexact fraction or a disabled exponent overflow. This bit is not
sticky.
Floating-point result flags. This field is based on the value placed into the target register even if
that value is undefined. Refer to
Table 3-4
for specific bit settings.
15
Floating-point result class descriptor (C). Floating-point instructions other than the
compare instructions may set this bit with the FPCC bits, to indicate the class of the
result.
16:19
Floating-point condition code (FPCC). Floating-point compare instructions always
set one of the FPCC bits to one and the other three FPCC bits to zero. Other
floating-point instructions may set the FPCC bits with the C bit, to indicate the class
of the result. Note that in this case the high-order three bits of the FPCC retain their
relational significance indicating that the value is less than, greater than, or equal to
zero.
16
Floating-point less than or negative (FL or <)
17
Floating-point greater than or positive (FG or >)
18
Floating-point equal or zero (FE or =)
19
Floating-point unordered or NaN (FU or )
Reserved
1
FEX
2
VX
3
4
5
6
7
8
9
OX
UX
ZX
XX
VXSNAN
VXISI
VXIDI
VXZDZ
VXIMZ
VXVC
10
11
12
13
FR
14
FI
15:19
FPRF
20
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