
MPC509
USER’S MANUAL
DEVELOPMENT SUPPORT
Rev. 15 June 98
MOTOROLA
8-25
8.3.2.1 Development Port Shift Register
The development port shift register is a 35-bit shift register. Instructions and data are
shifted into it serially from DSDI. These instructions or data are then transferred in par-
allel to the processor or the trap enable control register (TECR).
When the processor enters debug mode, it fetches instructions from the development
port shift register. These instructions are serially loaded into the shift register from
DSDI.
When the processor is in debug mode, data is transferred to the CPU by shifting it into
the shift register. The processor then reads the data as the result of executing a “move
from special-purpose register DPDR” (development port data register) instruction.
In debug mode, data is also parallel loaded into the development port shift register
from the CPU by executing a “move to special purpose register DPDR” instruction. It
is then shifted out serially to PLLL/DSDO.
8.3.2.2 Trap Enable Control Register
The trap enable control register (TECR) is a nine-bit register that is loaded from the
development port shift register. The contents of the TECR are used to drive the six trap
enable signals, the two breakpoint signals, and the VSYNC signal to the processor.
Trap-enable transmissions to the development port cause the appropriate bits of the
development port shift register to be transferred to the control register.
8.3.3 Development Port Clock Mode Selection
All of the development port serial transmissions are clocked transmissions. The trans-
mission clock can be either synchronous or asynchronous with the system clock
(CLKOUT). The development port supports three methods for clocking the serial
transmissions. The first method allows the transmission to occur without being exter-
nally synchronized with CLKOUT but at more restricted data rates. The two faster
communication methods require the clock and data to be externally synchronized with
CLKOUT.
The first clock mode is called asynchronous clockedsince the input clock (DSCK) is
asynchronous with CLKOUT. The input synchronizers on the DSCK and DSDI pins
sample the inputs to ensure that the signals used internally have no metastable oscil-
lations. To be sure that data on DSDI is sampled correctly, transitions on DSDI must
occur a setup time ahead of the rising edge of DSCK. Data on DSDI must also be held
for one CLKOUT cycle plus one hold time after the rising edge of DSCK. This ensures
that after the signals have passed through the input synchronizers, the data will be
valid at the rising edge of the serial clock even if DSCK and DSDI do not meet the
setup and hold time requirements of the pins.
Asynchronous clocked mode allows communications with the port from a development
tool that does not have access to the CLKOUT signal or where the CLKOUT signal has
been delayed or skewed. Because of the asynchronous nature of the inputs and the
setup and hold time requirements on DSDI, this clock mode must be clocked at a fre-
quency less than or equal to one third of CLKOUT.