Table
Title
Page
MPC509
USER’S MANUAL
LIST OF TABLES
Rev. 15 June 1998
MOTOROLA
xvii
5-46 Reset Status Register Bit Settings ................................................................... 5-93
5-47 Reset Behavior for Different Clock Modes ....................................................... 5-97
5-48 Pin Configuration During Reset......................................................................... 5-98
5-49 Data Bus Reset Configuration Word .............................................................. 5-100
5-50 SIU Port Registers Address Map..................................................................... 5-102
5-51 Port M Pin Assignments .................................................................................. 5-104
5-52 Port A Pin Assignments ................................................................................. 5-105
5-53 Port B Pin Assignments ................................................................................. 5-105
5-54 Port I Pin Assignments .................................................................................... 5-107
5-55 Port J Pin Assignments.................................................................................... 5-107
5-56 Port K Pin Assignments................................................................................... 5-108
5-57 Port L Pin Assignments ................................................................................... 5-108
6-1 PCU Address Map ............................................................................................... 6-2
6-2 PCUMCR Bit Settings ......................................................................................... 6-3
6-3 SWCR/SWTC Bit Settings .................................................................................. 6-5
6-4 IMB2 Interrupt Multiplexing.................................................................................... 6-8
6-5 Interrupt Controller Registers................................................................................. 6-8
6-6 PITQIL Bit Settings ........................................................................................... 6-10
6-7 Port Q Pin Assignments....................................................................................... 6-12
6-8 Port Q Edge Select Field Encoding..................................................................... 6-12
7-1 MPC509 SRAM Module Addresses....................................................................... 7-1
7-2 SRAMMCR Bit Settings ...................................................................................... 7-3
8-1 Program Trace Cycle Attribute Encodings............................................................. 8-3
8-2 Fetch Show Cycles Control ................................................................................... 8-4
8-3 VF Pins Instruction Encodings ............................................................................ 8-5
8-4 VF Pins Queue Flush Encodings........................................................................... 8-6
8-5 VFLS Pin Encodings.............................................................................................. 8-6
8-6 Cycle Type Encodings........................................................................................... 8-7
8-7 Detecting the Trace Buffer Starting Point............................................................ 8-10
8-8 I-bus Watchpoint Programming Options.............................................................. 8-17
8-9 L-Bus Data Events ............................................................................................. 8-18
8-10 L-Bus Watchpoints Programming Options......................................................... 8-19
8-11 Trap Enable Data Shifted Into Development Port Shift Register....................... 8-31
8-12 Breakpoint Data Shifted Into Development Port Shift Register ......................... 8-31
8-13 CPU Instructions/Data Shifted into Shift Register.............................................. 8-31
8-14 Status Shifted Out of Shift Register — Non-Debug Mode................................. 8-32
8-15 Status/Data Shifted Out of Shift Register .......................................................... 8-32
8-16 Sequencing Error Activity .................................................................................. 8-33