
MPC509
USER’S MANUAL
SIGNAL DESCRIPTIONS
Rev. 15 June 98
MOTOROLA
2-5
BURST
EBI
Output
If asserted, indicates cycle is a burst cycle.
Continuously-running clock. All signals driven on the E-bus must be syn-
chronized to the rising edge of this clock.
Cancel reservation. Each RCPU has its own CR signal. When asserted,
instructs the bus master to clear its reservation.
CLKOUT
EBI
Output
CR
EBI
Input
CSBOOT
Chip
Selects
Chip
Selects
Output
Chip select of system boot memory.
CS[0:11]
Output
Chip-select signals for external memory devices.
CT[0:3]
EBI
Output
Cycle type signals. Indicate what type of bus cycle the bus master is ini-
tiating.
32-bit data bus.
Data strobe. Asserted by EBI at the end of a chip-select-controlled bus
cycle after the chip-select unit asserts the internal TA signal or the bus
monitor timer asserts the internal TEA signal. Also asserted at the end
of a show cycle. Used primarily by development tools.
Development serial clock. Used to clock data shifted into or out of devel-
opment serial port.
Development serial data in. Used to shift development serial data into
the development port shift register.
Development serial data out. Used to shift development serial data out
of the development port shift register.
Provides a clock reference output with a frequency equal to the crystal
oscillator frequency, taken from the PLL feedback signal.
Connection for external crystal to the internal oscillator circuit, or clock
input.
Interrupt request inputs.
Clock mode. The state of this signal and that of V
DDSN
during reset de-
termine the source of the system clock (normal operation, 1:1 mode,
PLL bypass mode, or special test mode). Refer to
Table 5-32
in
SEC-
TION 5 SYSTEM INTERFACE UNIT
for details.
Port A discrete output signals.
Port B discrete output signals.
Power-down wakeup to external power-on reset circuit.
Port I discrete input/output signals.
Port J discrete input/output signals.
Port K discrete input/output signals.
Port L discrete input/output signals.
Port M discrete input/output signals.
Port Q discrete input/output signals.
Indicates whether phase-locked loop is locked.
Hard reset. When asserted, devices on the bus must reset.
Reset output signal. Asserted by MCU during reset. When asserted, in-
structs all devices monitoring this signal to reset all parts within them-
selves that can be reset by software.
Transfer acknowledge. When asserted, indicates the slave has received
the data during a write cycle or returned the data during a read cycle.
DATA[0:31]
EBI
Input/Output
DS
EBI
Output
DSCK
Dev.
Support
Dev.
Support
Dev.
Support
Input
DSDI
Input
DSDO
Output
ECROUT
Clocks
Output
EXTAL
Clocks
Input
IRQ[0:6]
PCU
Input
MODCLK
Clocks
Input
PA[0:7]
PB[0:7]
PDWU
PI[0:7]
PJ[0:7]
PK[0:7]
PL[2:7]
PM[3:7]
PQ[0:6]
PLLL
RESET
Ports
Ports
Clocks
Ports
Ports
Ports
Ports
Ports
PCU
Clock
EBI
Output
Output
Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
Input
RESETOUT
EBI
Output
TA
EBI
Input
Table 2-5 Signal Descriptions (Continued)
Mnemonic
Module
Direction
Description