MPC509
USER’S MANUAL
SYSTEM INTERFACE UNIT
Rev. 15 June 98
MOTOROLA
5-13
Table 5-5 EBI Signal Descriptions
Mnemonic
Direction
Description
Address Phase Signals
32-bit address bus. Least significant two bits (ADDR[30:31]) are not
pinned out; they can be determined from the BE[0:3] pins. ADDR0 is the
most significant bit. Address bus is driven by the bus master to index the
bus slave.
Transfer start. This address control signal is asserted for one clock cycle
at the beginning of a bus access by the bus master.
Write/read. When this address attribute is asserted, a write cycle is in
progress. When negated, a read cycle is in progress. For use of WR dur-
ing show cycles, refer to
SECTION 8 DEVELOPMENT SUPPORT
.
Byte enables. These address attribute signals indicate which byte within
a word is being accessed. External memory chips can use these signals
to determine which byte location is enabled.
Table 5-7
shows the encod-
ings for these pins during accesses to 32-bit and 16-bit ports.
A device need only observe the byte enables corresponding to the data
lanes on which it resides. For example, a device on data lane DATA[0:7]
should use BE0, and a device on DATA[0:15] should use BE[0:1]. The
device should not respond to the bus cycle unless its byte enables are
active at the start of the bus cycle.
Address types. These address attribute signals define addressed space
as user or supervisor, data or instruction. Refer to
Table 5-6
for encod-
ings. These signals have the same timing as ADDR[0:29].
Cycle type signals. These address attribute signals indicate what type of
bus cycle the bus master is initiating. Used for development support. Re-
fer to
Table 5-14
for encodings.
Burst cycle. This address attribute indicates that the transfer is a burst
transfer. If a burst access is burst-inhibited by the slave, the BURST pin
is driven during each single-beat (decomposed) cycle.
Address acknowledge. When asserted, indicates the slave has received
the address from the bus master. This signal terminates the address
phase of a bus cycle. When the bus master receives this signal from the
slave, the master can initiate another address transfer. This signal must
be asserted at the same time or prior to TA assertion.
Address retry. This is an address phase termination signal. It is de-
signed to resolve deadlock cases on hierarchical bus structures or for
error-correcting memories. ARETRY assertion overrides AACK asser-
tion and causes the SIU to re-arbitrate and to re-run the bus cycle.
Burst inhibit. When asserted, indicates the slave does not support burst
mode. Sampled at same time as AACK. If BI is asserted, the SIU trans-
fers the burst data in multiple cycles and increments the address for the
slave in order to complete the burst transfer.
Data Phase Signals
32-bit data bus. DATA0 is most significant bit; DATA31 is the least sig-
nificant bit. During small-port accesses, data resides on DATA[0:15].
ADDR[0:29]
M
→
S
TS
M
→
S
WR
M
→
S
BE[0:3]
M
→
S
AT[0:1]
M
→
S
CT[0:3]
M
→
S
BURST
M
→
S
AACK
S
→
M
ARETRY
S, A
→
M
BI
S
→
M
DATA[0:31]
M
S