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參數(shù)資料
| 型號： | MCZ33797EKR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 6/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SQUIB DRIVER 2CHAN 32-SOIC |
| 標準包裝： | 1,000 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 32-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 32-SOIC |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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Analog Integrated Circuit Device Data
14
Freescale Semiconductor
33797
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V VDD 5.25 V; 7.0 V VVFIRE_XX 35 V; VVDIAG_X = VVFIRE_XX;
FEN 1 = FEN 2 = VDD; RR_LIMIT_X = 10 k ±1%, RR_DIAG = 10 k ±1%, -40 C TA +85 C, GND = 0, unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SERIAL INTERFACE
CLK Cycle Time (1/FCLK) (18)
tCYC
200
–
ns
CLK High Time (18)
VCLK > VDD x 70%
tHI
73
–
ns
CLK Low Time (18)
VCLK < VDD x 20%
tLO
73
–
ns
Clock Rise Time (18)
VCLK = 20% VDD to 70% VDD, CLOAD = 100 pF
tRISE
–
20
ns
Clock Fall Time (18)
VCLK = 70% VDD to 20% VDD, CLOAD = 100 pF
tFALL
–
20
ns
Data Out Rise Time (19)
VDO = 20% VDD to 70% VDD, CLOAD = 100 pF
tR
–
20
ns
Data Out Fall Time (19)
VDO = 70% VDD to 20% VDD, CLOAD = 100 pF
tF
–
20
ns
Chip Select Setup Time (19)
CSB
Before CLK
tLEAD
73
–
ns
Chip Select Hold Time (19)
CLK
Before CSB
tLAG
73
–
ns
Data In Setup Time (19)
D1 Valid Before CLK
tSU
30
–
ns
Data In Hold Time (19)
D1 Hold Time After CLK
tH
30
–
ns
Data Out Access Time (19)
CSB
to D0 Valid
tA
–
73
ns
Data Out Disable Time (19)
CSB
to D0 HI-Z
tDIS
–
73
ns
Data Out Valid Time (19)
CLK
to D0 Valid, CLOAD = 100 pF
tV
–
75
ns
Data Out Hold Time (19)
D0 held After CLK
tHO
0.0
–
ns
Diagnostic Delay Time (Between Two Successive Commands)
tDIAG
2.5
–
s
Notes
18
Determined by Design
19
Guaranteed by Characterization
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