System Integration Module (SIM)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
6-12
Freescale Semiconductor
If an interrupt timeout value is programmed in WIRR, and this value is reached prior to the reset timeout
value, WER[WIE] is set and a maskable interrupt is issued at the level defined by ICR4[SWTOIPL].
The software watchdog consists of a 15-bit counter with a 15-bit prescaler. It counts up to a maximum of
32768, with a resolution of 32768 clock periods. Thus, at 66 MHz, the resolution of the watchdog is 0.5
msec, with a maximum timeout period of 32768 * 32768 = 230 clock periods or 16.267 S.
Timeout = (WRRR +1) * 32768 clocks
6.2.8.1
Watchdog Reset Reference Register (WRRR)
The watchdog reset reference register (WRRR),
Figure 6-8, contains the reference value for the software
watchdog timeout causing a reset.
6.2.8.2
Watchdog Interrupt Reference Register (WIRR)
The watchdog interrupt reference register (WIRR),
Figure 6-9, contains the reference value for the
software watchdog timeout causing an interrupt.
15
10
Field
REF
EN
Reset
1111_1111_1111_1110
R/W
Address
MBAR + 0x280
Figure 6-8. Watchdog Reset Reference Register (WRRR)
Table 6-9. WRRR Field Descriptions
Bits
Field
Description
15–1
REF
Reference value. This field determines the reset timeout value.Reset initializes this register to 0xFFFE,
disabling the watchdog timer and setting it to the maximum timeout value.
0
EN
Enable watchdog. When enabled, software should periodically write to WCR to avoid reaching the reset
reference value.
0 Watchdog timer disabled.
1 Watchdog timer enabled.
15
10
Field
REF
IEN
Reset
1111_1111_1111_1110
R/W
Address
MBAR + 0x284
Figure 6-9. Watchdog Interrupt Reference Register (WIRR)