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Signal Descriptions
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
19-37
19.17.9 Debug Data (DDATA[3:0])
Debug data signals (DDATA[3:0]) display captured processor data and breakpoint status.
19.17.10 Device Test Enable (TEST)
TEST is used to put the device into various manufacturing test modes. It should be tied to VDD for normal
operation.
19.18 Operating Mode Configuration Pins
The MCF5272 has four mode-select signals, some of which are shared with output signals used during
normal device operation. These signals are HI-Z, QSPI_Dout/WSEL, QSPI_CLK/BUSW1, and
QSPI_CS0/BUSW0. BYPASS is a Freescale test mode signal and should never have a pull-down resistor.
The remaining three mode-select signals must each have a 4.7-K pull-up or pull-down resistor. These
signals are sampled on the rising edge of Reset Output (RSTO).
Table 19-7. Processor Status Encoding
PST[3:0]
Definition
0000
Continue execution
0001
Begin execution of an instruction
0010
Begin execution of PULSE instruction or WDDATA.
0011
Entry into user mode
0100
Begin execution of PULSE instruction
0101
Begin execution of taken branch
0110
Reserved
0111
Begin execution of RTE instruction
1000
Begin 1 byte transfer on DDATA
1001
Begin 2 byte transfer on DDATA
1010
Begin 3 byte transfer on DDATA
1011
Begin 4 byte transfer on DDATA
1100 1
1 These encodings are asserted for multiple cycles.
Exception processing
Emulator mode entry exception processing
Processor is stopped, waiting for an interrupt
Processor is halted