Electrical Characteristics
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
23-18
Freescale Semiconductor
23.6.2
MII Transmit Signal Timing (E_TxD[3:0], E_TxEN, E_TxER,
E_TxCLK)
The transmitter functions correctly up to a E_TxCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
E_TxCLK frequency.
The transmit outputs (E_TxD[3:0], E_TxEN, E_TxER) can be programmed to transition from either the
rising or falling edge of E_TxCLK, and the timing is the same in either case. This options allows the use
of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Figure 23-12. MII Transmit Signal Timing Diagram
Table 23-12. MII Transmit Signal Timing
Num
Characteristic1
1 E_TxCLK, ETxD0, and E_TxEN have the same timing in 10 Mbit 7-wire interface mode.
Min
Max
Unit
M5
E_TxCLK to E_TxD[3:0], E_TxEN, E_TxER invalid
5
—
nS
M6
E_TxCLK to E_TxD[3:0], E_TxEN, E_TxER valid
—
25
nS
M7
E_TxCLK pulse-width high
35%
65%
E_TxCLK period
M8
E_TxCLK pulse-width low
35%
65%
E_TxCLK period
M6
E_TxCLK (input)
E_TxD[3:0] (outputs)
E_TxEN
E_TxER
M5
M7
M8