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Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-5
Figure 13-5. GCI/IDL B Data Transmit Register Multiplexing
13.2.3
GCI/IDL B- and D-Channel Bit Alignment
Unencoded voice is normally presented on the physical line most significant bit first (left aligned). See the
MC145484 data sheet for an example. Accordingly, the MCF5272 normally assumes incoming data are
left-aligned.
However, this convention is reversed when the data stream is HDLC (high-level data link control)
encoded. HDLC-stuffing and unstuffing are done by counting bits from the lsb. The look-up table in the
software HDLC on this device transmits the lsb first.
13.2.3.1
B-Channel Unencoded Data
Because unencoded voice data appears on the physical interface most significant bit (msb) first, the msb
is left aligned in the transmit and receive shift register; that is, the first bit of B-channel received data is
The CPU uses longword (32-bit) registers (like P0B1RR) to communicate B-channel data to/from the
PLIC. These registers are loaded by concatenating four of the 8-bit/8-KHz frames. The four frames are
aligned sequentially as shown in
Figure 13-6, with the first frame in the most significant byte (MSB)
position, and the fourth frame taking the least significant byte (LSB) position. See
Section 13.5.1, “B18 bits
MUX
Internal Bus
8-KHz Rate
Shift Register
2-KHz transfer and interrupt
Shadow Register
8 bits
START
END
32 bits
32
B1, B2 Transmit
Data Register