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參數(shù)資料
| 型號： | MBM29DL163TD12PBT |
| 廠商： | FUJITSU LTD |
| 元件分類： | PROM |
| 英文描述： | 1M X 16 FLASH 3V PROM, 120 ns, PBGA48 |
| 封裝： | PLASTIC, FBGA-48 |
| 文件頁數(shù)： | 59/76頁 |
| 文件大小： | 1146K |
| 代理商： | MBM29DL163TD12PBT |
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MBM29DL16XTD/BD-70/90/12
62
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also Table 14 and Figure 12.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
Table 14 Toggle Bit Status
Note: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-
erase suspend sector address will indicate logic “1” at the DQ2 bit.
RY/BY
Ready/Busy
The MBM29DL16XTD/BD provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29DL16XTD/BD are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to Figures 13 and 14 for a detailed timing diagram. The RY/BY
pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL16XTD/BD devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0
to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer
to Figures 15, 16 and 17 for the timing diagram.
Data Protection
The MBM29DL16XTD/BD are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
Mode
DQ7
DQ6
DQ2
Program
DQ7
Toggle
1
Erase
0
Toggle
Toggle (Note)
Erase-Suspend Read
(Erase-Suspended Sector)
11
Toggle
Erase-Suspend Program
DQ7
Toggle
1 (Note)
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