參數(shù)資料
型號(hào): MB95F118JWPMC-GE1
廠商: Fujitsu Semiconductor America Inc
文件頁(yè)數(shù): 34/76頁(yè)
文件大?。?/td> 0K
描述: IC MCU 60K FLASH 2KB RAM 52LQFP
標(biāo)準(zhǔn)包裝: 1
系列: F²MC MB95110M
核心處理器: F²MC-8FX
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,LIN,SIO,UART/USART
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 39
程序存儲(chǔ)器容量: 60KB(60K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 52-LQFP
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 722 (CN2011-ZH PDF)
其它名稱(chēng): 865-1071
MB95110M Series
4
■ PRODUCT LINEUP
(Continued)
MB95117M
MB95F114MS/
MB95F116MS/
MB95F118MS
MB95F114NS/
MB95F116NS/
MB95F118NS
MB95F114MW/
MB95F116MW/
MB95F118MW/
MB95F114NW/
MB95F116NW/
MB95F118NW
MB95F114JS/
MB95F116JS/
MB95F118JS
MB95F114JW/
MB95F116JW/
MB95F118JW
Type
MASK
ROM
product
Flash memory product
ROM capacity*1
48 Kbytes
60 Kbytes (Max)
RAM capacity*1
2 Kbytes (Max)
Reset output
Yes/No
Yes
No
Option*
2
Clock system
Selectable
single/dual
clock*3
Single clock
Dual clock
Single
clock
Dual clock
Low voltage
detection reset
Yes / No
No
Yes
No
Yes
Clock
supervisor
Yes / No
No
Yes
CPU functions
Number of basic instructions
: 136
Instruction bit length
: 8 bits
Instruction length
: 1 to 3 bytes
Data bit length
: 1, 8, and 16 bits
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)
Interrupt processing time
: 0.6
s (at machine clock frequency 16.25 MHz)
Peripheral
functions
General
purpose
I/O ports
Single clock product : 39 ports (N-ch open drain : 2 ports, CMOS : 37 ports)
Dual clock product
: 37 ports (N-ch open drain : 2 ports, CMOS : 35 ports)
Programmable input voltage levels of port :
Automotive input level
/ CMOS input level / hysteresis input level
Time-base
timer
(1 channel)
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Watchdog
timer
Reset generated cycle
At main oscillation clock 10 MHz
: Min 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms
Wild register
Capable of replacing 3 bytes of ROM data
I2C
(1 channel)
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
UART/SIO
(1 channel)
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate
generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
Part number
Parameter
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參數(shù)描述
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