= 5.0 V ± 10%, AVss = Vss = 0.0 V, TA
參數(shù)資料
型號(hào)： MB95F118JWPMC-GE1
廠商： Fujitsu Semiconductor America Inc
文件頁(yè)數(shù)： 33/76頁(yè)
文件大?。?/td> 0K
描述： IC MCU 60K FLASH 2KB RAM 52LQFP
標(biāo)準(zhǔn)包裝： 1
系列： F²MC MB95110M
核心處理器： F²MC-8FX
芯體尺寸： 8-位
速度： 16MHz
連通性： I²C，LIN，SIO，UART/USART
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 39
程序存儲(chǔ)器容量： 60KB（60K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8/10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-LQFP
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 722 (CN2011-ZH PDF)
其它名稱： 865-1071
MB95110M Series
39
(2) Source Clock/Machine Clock
(Vcc
= 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it
becomes the machine clock. Further, the source clock can be selected as follows.
Main clock divided by 2
PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
Sub clock divided by 2
PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
Source clock (no division)
Source clock divided by 4
Source clock divided by 8
Source clock divided by 16
Parameter
Sym-
bol
Condi-
tions
Value
Unit
Remarks
Min
Typ
Max
Source clock
cycle time*1
(Clock before
setting division)
tSCLK
61.5
2000
ns
When using main clock
Min : FCH
= 8.125 MHz, PLL multiplied by 2
Max : FCH
= 1 MHz, divided by 2
7.6
61.0
s
When using sub clock
Min : FCL
= 32 kHz, PLL multiplied by 4
Max : FCL
= 32 kHz, divided by 2
Source clock
frequency
FSP
0.50
16.25
MHz When using main clock
FSPL
16.384
131.072
kHz
When using sub clock
Machine clock
cycle time*2
(Minimum
instruction
execution time)
tMCLK
61.5
32000
ns
When using main clock
Min : FSP
= 16.25 MHz, no division
Max : FSP
= 0.5 MHz, divided by 16
7.6
976.5
s
When using sub clock
Min : FSPL
= 131 kHz, no division
Max : FSPL
= 16 kHz, divided by 16
Machine clock
frequency
FMP
0.031
16.250
MHz When using main clock
FMPL
1.024
131.072
kHz
When using sub clock
FCH
(main oscillation)
FCL
(sub oscillation)
Devided by 2
Main PLL
× 1
× 2
× 2.5
× 4
Devided by 2
Sub PLL
× 2
× 3
× 4
SCLK
( source clock )
MCLK
( machine clock )
Clock mode select bit
( SYCC : SCS1, SCS0 )
Division
circuit
× 1
× 1/4
× 1/8
× 1/16
Outline of clock generation block
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MB95F118MW 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers
MB95F118MW/F118NW 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers
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