參數(shù)資料
型號: M37736EHBGS
廠商: Mitsubishi Electric Corporation
英文描述: PROM VERSION OF M37736EHBXXXGP
中文描述: PROM的版本M37736EHBXXXGP
文件頁數(shù): 61/96頁
文件大?。?/td> 1328K
代理商: M37736EHBGS
61
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Main clock : Oscillating
Sub clock : Stopped
I/O ports P7
7
and P7
6
f
2
: Main-clock side
: Main-clock side
Main clock : Oscillating
Sub clock : Stopped
I/O ports P7
7
and P7
6
f
2
: Main-clock side
: Stopped
Main clock : Stopped
Sub clock : Stopped
I/O ports P7
7
and P7
6
f
2
: Stopped
: Stopped
WIT instruction
Interrupt
STP instruction
Interrupt
X
C
is selected
(CM
4
= “1”)
Main clock : Oscillating
Sub clock : Oscillating
f
2
: Main-clock side
: Main-clock side
Main clock : Oscillating
Sub clock : Oscillating
f
2
: Main-clock side
(Note 2)
: Stopped
Main clock : Stopped
Sub clock : Stopped
f
2
: Stopped
: Stopped
WIT instruction
Interrupt
STP intrunction
Interrupt
Sub clock is selected as
system clock (Note 1)
(CM
3
= “1”)
Main clock : Oscillating
Sub clock : Oscillating
f
2
: Sub-clock side
: Sub-clock side
Main clock : Oscillating
Sub clock : Oscillating
f
2
: Sub-clock side (Note 2)
: Stopped
Main clock : Stopped
Sub clock : Stopped
f
2
: Stopped
: Stopped
WIT instruction
Interrupt
STP intrunction
Interrupt
Main clock
oscillation stops
(CM
2
= “1”)
Main clock : Stopped
Sub clock : Oscillating
f
2
: Sub-clock side
: Sub-clock side
Main clock :Stopped
Sub clock :Oscillating
f
2
: Sub-clock side (Note 2)
: Stopped
WIT instruction
Interrupt
Reset
Main clock is selected as
system clock (Note 1)
(CM
3
= “0”)
Main clock
oscillation starts
(CM
2
= “0”)
Notes1.
Before selecting the main/sub clock of which oscillation already starts as the system clock, use software
to fully stabilize the oscillation.
2.
When the system clock stop bit at wait state (CM
5
) is “1”, f
2
stops at wait state.
Main clock : Stopped
Sub clock : Stopped
f
2
: Stopped
: Stopped
STP instruction
Interrupt
Fig. 67 System clock state transition
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