參數(shù)資料
型號: M37736EHBGS
廠商: Mitsubishi Electric Corporation
英文描述: PROM VERSION OF M37736EHBXXXGP
中文描述: PROM的版本M37736EHBXXXGP
文件頁數(shù): 52/96頁
文件大?。?/td> 1328K
代理商: M37736EHBGS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
52
Fig. 61 Relationship between wait bit, wait selection bit, and access time
Wait bit
As shown in Figure 61, when the external memory area is accessed
with the wait bit (bit 2 of the processor mode register 0 at address
5E
16
) cleared to “0”, the access time can be extended compared with
no wait (the wait bit is “1”).
The access time is extended in two ways and this is selected with the
wait selection bit (bit 0 of the processor mode register 1 at address
5F
16
).
When this bit is “1”, the access time is 1.5 times compared to that for
no wait. When this bit is “0”, the access time is twice compared to
that for no wait.
At reset, the wait bit and the wait selection bit are “0”.
The accessing of internal memory area is always performed in the
no wait mode regardless of the wait bit.
The processor modes are described below.
Wait bit “1”
(No wait)
Wait bit “0”
(Wait 1)
Wait bit “0”
(Wait 0)
Internal clock
Port P2
ALE
Port P2
E or RDE,
WEL,WEH
ALE
Access time
Access time
Address
Data
Address
Data
Address
Data
Address
Data
Port P2
ALE
Access time
Address
Data
Address
SFR
RAM
Microprocessor
mode
The shaded area is the external memory area.
However, in the external bus mode B, banks 10
16
to FF
16
cannot be accessed.
Additionally, the evaluation chip mode cannot also be
selected.
SFR
00
16
80
16
FFFFFF
16
RAM
ROM
Memory expansion
mode
1000
16
1FFFF
16
FFF
16
SFR
RAM
Evaluation
chip mode
2
16
A
16
C
16
E or RDE,
WEL,WEH
E or RDE,
WEL,WEH
Fig. 60 External memory area for each processor mode
(1) Single-chip mode [00]
Single-chip mode is entered by connecting the CNVss pin to Vss and
starting from reset. Ports P0 to P4 all function as normal I/O ports.
Port P4
2
can output clock
register 0 to “1”. For clock
In this mode, signal
E
is output from pin
E/RDE
. Signal
E
output,
however, can be stopped by setting the signal output disable selection
bit (bit 6 of the oscillation circuit control register 0) to “1”, and it is
possible to switch the
E
pin function to “L” output. Table 7 shows the
function of the signal output disable selection bit.
1
by setting bit 7 of the processor mode
1
, refer to Figure 66.
_
(2) Memory expansion mode [01]
Memory expansion mode is entered by setting the processor mode
bits to “01” after connecting the CNVss pin to Vss and starting from
reset.
The function differs between the external bus mode A and the external
bus mode B.
External bus mode A
Pin
E/RDE
becomes the output pin for signal
E
.
_
E
is an enable signal and is “L” during the data/instruction code read
or data write term. When the internal memory area is read or written,
_
E
can be fixed to “H” by setting the signal output disabe selection bit
(bit 6 of the oscillation circuit control register 0) to “1”.
Port P0 becomes an address output pin and loses its I/O port function.
Port P1 has two functions depending on the level of the BYTE pin. In
both cases, the I/O port function is lost.
When the BYTE pin level is “L”, port P1 functions as an address
output pin while
E
is “H” and as an odd address data I/O pin while
E
is “L”. However, if an internal memory is read, external data is ignored
while
E
is “L”.
When the BYTE pin level “H”, port P1 functions as an address output
pin.
_
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