參數(shù)資料
型號(hào)： M37736EHBGS
廠商： Mitsubishi Electric Corporation
英文描述： PROM VERSION OF M37736EHBXXXGP
中文描述： PROM的版本M37736EHBXXXGP
文件頁(yè)數(shù)： 12/96頁(yè)
文件大?。?/td> 1328K
代理商： M37736EHBGS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
12
INTERRUPTS
Table 1 shows the interrupt sources and the corresponding interrupt
vector addresses. Reset is also treated as a source of interrupt and
___
DBC
is an interrupt used only for debugging.
Interrupts other than reset,
DBC
, watchdog timer, zero divide, and
BRK instruction all have their respective interrupt control registers.
Table 2 shows the addresses of the interrupt control registers and
Figure 6 shows the bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by hardware during
reset or when processing an interrupt. Also, interrupt request bits
DBC
and watchdog timer can be cleared by software.
___
___
INT
0
to
INT
2
are external interrupts, and whether to cause an interrupt
at the input level (level sense) or at the edge (edge sense) can be
selected with the level sense/edge sense selection bit. Furthermore,
the polarity of the interrupt input can be selected with a polarity
selection bit.
In the
INT
___
__
__
from the
INT
2
pin or the
KI
0
–
KI
3
pins can be selected by bit 7 of the
port function control register (refer to Figure 11).
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupts are caused
simultaneously is partially fixed by hardware, but it can also be
adjusted by software as shown in Figure 7. The hardware priority is
fixed as follows:
reset >
DBC
> watchdog timer > other interrupts
Table 1. Interrupt sources and the interrupt vector addresses
Interrupts
A-D/UART2 trans./rece.
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
2
/Key input
___
1
___
0
DBC
(unusable)
BRK instruction
Zero divide
Reset
Fig. 6 Interrupt control register bit configuration
7
Interrupt priority level selection bits
Interrupt request bit
0 : No interrupt
1 : Interrupt
6
5 4
3
2 1
0
Interrupt control register configuration for timers A0 to A4, timers B0 to B2, UART0, UART1 and
A-D/UART2 trans./rece.
7
Interrupt priority level selection bits
Interrupt request bit
0 : No interrupt
1 : Interrupt
Polarity selection bit
0 : Interrupt request bit is set at “H” level for level sense or at the falling
edge for edge sence.
1 : Interrupt request bit is set at “L” level for level sense or at the rising
edge for edge sense.
Level sense/edge sense selection bit
0 : Edge sense
1 : Level sense
6
5 4
3
2 1
0
Interrupt control register configuration for
INT
0
to
INT
2
/Key input
Vector addresses
00FFD6
16
00FFD8
16
00FFDA
16
00FFDC
16
00FFDE
16
00FFE0
16
00FFE2
16
00FFE4
16
00FFE6
16
00FFE8
16
00FFEA
16
00FFEC
16
00FFEE
16
00FFF0
16
00FFF2
16
00FFF4
16
00FFF6
16
00FFF8
16
00FFFA
16
00FFFC
16
00FFFE
16
00FFD7
16
00FFD9
16
00FFDB
16
00FFDD
16
00FFDF
16
00FFE1
16
00FFE3
16
00FFE5
16
00FFE7
16
00FFE9
16
00FFEB
16
00FFED
16
00FFEF
16
00FFF1
16
00FFF3
16
00FFF5
16
00FFF7
16
00FFF9
16
00FFFB
16
00FFFD
16
00FFFF
16
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