參數(shù)資料
型號(hào)： M-ORT82G52BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁(yè)數(shù)： 7/94頁(yè)
文件大?。?/td> 2104K
代理商： M-ORT82G52BM680-DB
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
15
logic and record status. These bits are passed to the core using the FPGA System Bus and are described in later
sections of this data sheet Table 8.
The low-speed transmit interface consists of a clock and 4 data bytes, each with an accompanying control bit. The
data bytes are conveyed to the MUX via the TWDxx[31:0] ports (where xx represents the channel label [AA,...,BD]).
The control bits are TCOMMAx[3:0] which dene whether the input byte is to be interpreted as data or as a special
character and TBIT9xx[3:0] which are used to force negative disparity encoding. The data and control signals are
synchronized to the transmit clock, TSYS_CLK_xx. Both the data and control are strobed into the core on the rising
edge of TSYS_CLK_xx.
The MUX is responsible for taking 40 bits of data/control at the low-speed transmit interface and up-converting it to
10 bits of data/control at the SERDES transmit interface. The MUX has 2 clock domains - one based on the clock
received from the SERDES block and a second that comes from the FPGA at 1/4 the frequency of the SERDES
clock. The time sequence of interleaving data/control values is shown in Figure 4 below.
Figure 4. Transmit MUX Block Timing - Single Channel
SERDES Block
The SERDES block accepts either 8-bit unencoded data or 10-bit encoded data at the parallel input port from the
MUX/DEMUX block. It also accepts the reference clock at the REFCLK_[A:B] input and uses this clock to synthe-
size the internal high-speed serial bit clock.
The internal STBC311xx clock is derived from the reference clock. The frequency of this clock depends on the set-
ting of the half-rate/full-rate control bit setting the mode of the SERDES and the frequency of the REFCLK_[A:B]
and/or that of the high-speed serial data. A falling edge on the STBC311xx clock port will cause a new data charac-
ter to be transferred into the SERDES block. The latency from the SERDES block input to the high-speed serial
output is 5 STBC311xx clock cycles, as shown in Figure 5.
pq
r
s
t
xyz
STBDxx[9:0]
LATENCY = 4 TSYS_CLK_xx CLOCKS
TWDxx[31:24],
TSYS_CLK_xx
s
8
r
8
z
8
y
8
10-bit wide data
TWDxx[23:16],
TWDxx[15:8],
r
7-0,
y
7-0,
TCOMMAxx[3]
TCOMMAxx[2]
TCOMMAxx[1]
TCOMMAxx[0]
TWDxx[7:0],
s
7-0,
z
7-0,
TBIT9xx[0]
TBIT9xx[1]
TBIT9xx[2]
TBIT9xx[3]
q
9
r
9
s
9
z
9
y
9
x
9
p
7-0,
p
8
t
7-0,
q
8
t
8
x
8
q
7-0,
x
7-0,
p
9
t
9
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