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| 型號(hào)： | M-ORT82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 52/94頁 |
| 文件大?。?/td> | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
56
30807 -
30907
[0:7]
Reserved for future use
30814 - Ax
30914 - Bx
[0]
xA & xB
[1] xC & xD
SYNC2_[A:B][1:2]
OVFL
Multi-Channel Overow Status. When SYNC2_[A:B][1:2]OVFL=1, dual-
channel synchronization FIFO overow has occurred.
SYNC2_[A:B][1:2]OVFL=0 on device reset.
[2]
SYNC4_
[A:B]OVFL
Multi-Channel Overow Status. When SYNC4_[A:B]OVFL=1, quad-
channel synchronization FIFO overow has occurred.
SYNC4_[A:B]OVFL=0 on device reset.
[3]
xA & xB
[4] xC & xD
SYNC2_[A:B][1:2]
OOS
Multi-Channel Out-Of-Sync Status. When SYNC2_[A:B][1:2] OOS=1,
dual-channel synchronization has failed.
SYNC2_[A:B][1:2] OOS on device reset.
[5]
SYNC4_[A:B]_OO
S
Multi-Channel Out-Of-Sync Status. When SYNC4_[A:B]_OOS=1, quad-
channel synchronization has failed.
SYNC4_[A:B]_OOS=0 on device reset.
[6:7]
Reserved for future use
30815
30915
[0:7]
Reserved for future use
30816
30916
[0:7]
Reserved for future use
30817
30917
[0:7]
Reserved for future use
30824
30924
[0:7]
Reserved for future use
Status Registers (Read Only), xx=[AA, ...,BD]
30804 - Ax
30904 - Bx
[0:1]
xA
[2:3]
xB
[4:5]
xC
[6:7]
xD
XAUISTAT_xx[0:1]
00
XAUI Status Register. Status of XAUI link state machine for Channel xx
00—No synchronization.
10—Synchronization done.
01,11—Not used.
XAUISTAT_xx[0:1] = 00 on device reset.
30805 - Ax
30905 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
DEMUXWAS_xx
00
Status of Word Alignment. When DEMUX_WAS_xx=1, word alignment is
achieved for Channel xx.
DEMUX_WAS_xx=0 on device reset.
[4]xA
[5]xB
[6]xC
[7]xD
CH248_SYNC_xx
Status of Channel Alignment. When CH248_SYNC_xx=1, multi-channel
alignment is achieved for Channel xx.
CH248_SYNC_xx=0 on device reset.
30806
30906
[0:7]
Reserved for future use
30807
30907
[0:7]
Reserved for future use
Table 20. Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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