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| 型號： | M-ORT82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 65/94頁 |
| 文件大?。?/td> | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
68
This section describes device I/O signals to/from the embedded core.
Table 30. FPSC Function Pin Descriptions
Symbol
I/O
Description
Common Signals for Both SERDES Quad A and B
PASB_RESETN
I
Active low reset for the embedded core. All non-SERDES specic registers
(addresses 308***, 309***, 30A***) in the embedded core are not reset.
PASB_TRISTN
I
Active low 3-state for embedded core output buffers.
PASB_PDN
I
Active low power down of all SERDES blocks and associated I/Os.
PASB_TESTCLK
I
Clock input for BIST and loopback test.
PBIST_TEST_ENN
I
Selection of PASB_TESTCLK input for BIST test.
PLOOP_TEST_ENN
I
Selection of PASB_TESTCLK input for loopback test.
PMP_TESTCLK
I
Clock input for microprocessor in test mode.
PMP_TESTCLK_ENN
I
Selection of PMP_TESTCLK in test mode.
PSYS_DOBISTN
I
Input to start BIST test.
PSYS_RSSIG_ALL
O
Output result of BIST test.
SERDES Quad A and B Pins
REFCLKN_A
I
CML reference clock input—SERDES quad A.
REFCLKP_A
I
CML reference clock input—SERDES quad A.
REFCLKN_B
I
CML reference clock input—SERDES quad B.
REFCLKP_B
I
CML reference clock input—SERDES quad B.
REXT_A
—
Reference resistor—SERDES quad A.
REXT_B
—
Reference resistor—SERDES quad B.
REXTN_A
—
Reference resistor—SERDES quad A. A 3.32 K ± 1% resistor must be connected
across REXT_A and REXTN_A. This register should handle a current of 300
REXTN_B
—
Reference resistor—SERDES quad B. A 3.32 K ± 1% resistor must be connected
across REXT_B and REXTN_B. This register should handle a current of 300
HDINN_AA
I
High-speed CML receive data input—SERDES quad A, channel A.
HDINP_AA
I
High-speed CML receive data input—SERDES quad A, channel A.
HDINN_AB
I
High-speed CML receive data input—SERDES quad A, channel B.
HDINP_AB
I
High-speed CML receive data input—SERDES quad A, channel B.
HDINN_AC
I
High-speed CML receive data input—SERDES quad A, channel C.
HDINP_AC
I
High-speed CML receive data input—SERDES quad A, channel C.
HDINN_AD
I
High-speed CML receive data input—SERDES quad A, channel D.
HDINP_AD
I
High-speed CML receive data input—SERDES quad A, channel D.
HDINN_BA
I
High-speed CML receive data input—SERDES quad B, channel A.
HDINP_BA
I
High-speed CML receive data input—SERDES quad B, channel A.
HDINN_BB
I
High-speed CML receive data input—SERDES quad B, channel B.
HDINP_BB
I
High-speed CML receive data input—SERDES quad B, channel B.
HDINN_BC
I
High-speed CML receive data input—SERDES quad B, channel C.
HDINP_BC
I
High-speed CML receive data input—SERDES quad B, channel C.
HDINN_BD
I
High-speed CML receive data input—SERDES quad B, channel D.
HDINP_BD
I
High-speed CML receive data input—SERDES quad B, channel D.
SERDES quad A and B Pins
HDOUTN_AA
O
High-speed CML transmit data output—SERDES quad A, channel A.
HDOUTP_AA
O
High-speed CML transmit data output—SERDES quad A, channel A.
HDOUTN_AB
O
High-speed CML transmit data output—SERDES quad A, channel B.
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