參數(shù)資料
型號(hào)： M-ORT82G52BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁數(shù)： 60/94頁
文件大小： 2104K
代理商： M-ORT82G52BM680-DB
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
63
HSI Electrical and Timing Characteristics
Table 24. Reference Clock Specications (REFINP and REFINN)
Table 25. Channel Output Jitter (1.25 Gbits/s) - Half Rate Mode
Table 26. Channel Output Jitter (2.5 Gbits/s) Full Rate Mode
Table 27. Serial Output Timing and Levels (CML I/O)
Parameter
Min
Typ
Max
Unit
Frequency Range
100
—
185
MHz
Frequency Tolerance
– 100
—
100
ppm
Duty Cycle (Measured at 50% Amplitude Point)
40
50
60
%
Rise Time
—
500
1000
ps
Fall Time
—
500
1000
ps
P–N Input Skew
—
75
ps
Differential Amplitude
500
800
2 x VDD
mVp-p
Common Mode Level
Vsingle-ended/2
0.75
VDD15 – (Vsingle-ended/2)
V
Single-Ended Amplitude
250
400
VDD15
mVp-p
Input Capacitance (at REFINP)
—
5
pF
Input Capacitance (at REFINPIT)
—
3
pF
Inband (< 10 MHz) Jitter (2.5 Gbits/s)
—
30
psp-p
Inband (< 10 MHz) Jitter (1.25 Gbits/s)
—
60
psp-p
Note: Additional (<10 MHz) REFCLK jitter will increase the total transmit output jitter.
Note: The frequency tolerance is important when separate reference clocks are used for the transmitter that is driving the receive
Parameter
Min
Typ
Max
Unit
Deterministic
—
0.08
UIp-p
Random
—
0.12
UIp-p
Total
—
0.20
UIp-p
Parameter
Min
Typ
Max
Unit
Deterministic
—
0.10
UIp-p
Random
—
0.14
UIp-p
Total
—
0.24
UIp-p
Parameter
Min
Typ
Max
Unit
Rise Time (20%—80%)
50
80
110
ps
Fall Time (80%—20%)
50
80
110
ps
Common Mode
VDDOB –0.30
VDDOB –0.25
VDDOB –0.15
V
Differential Swing (Full Amplitude)
800
900
1100
mVp-p
Differential Swing (Half Amplitude)
400
500
600
mVp-p
Output Load
—
50
—
Note: Differential swings are based on direct CML to CML connections.
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