參數(shù)資料
型號: LSM303DLHTR
廠商: STMICROELECTRONICS
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PBGA28
封裝: 5 X 5 MM, 1 MM HEIGHT, ROHS COMPLIANT, PLASTIC, LGA-16
文件頁數(shù): 6/47頁
文件大?。?/td> 585K
代理商: LSM303DLHTR
Module specifications
LSM303DLH
14/47
Doc ID 16941 Rev 1
2.3
Communication interface characteristics
2.3.1
Accelerometer sensor I2C - inter IC control interface
Subject to general operating conditions for Vdd and top.
Figure 3.
I2C slave timing diagram (b)
Table 5.
I2C slave timing values
Symbol
Parameter
I2C standard mode (1)
I2C fast mode (1)
Unit
Min
Max
Min
Max
f(SCL)
SCL clock frequency
0
100
0
400
KHz
tw(SCLL)
SCL clock low time
4.7
1.3
s
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
ns
th(SDA)
SDA data hold time
0.01
3.45
0.01
0.9
s
tr(SDA) tr(SCL)
SDA and SCL rise time
1000
20 + 0.1Cb
(2)
300
ns
tf(SDA) tf(SCL)
SDA and SCL fall time
300
20 + 0.1Cb
(2)
300
th(ST)
START condition hold time
4
0.6
s
tsu(SR)
Repeated START condition
setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
tw(SP:SR)
Bus free time between STOP
and START condition
4.7
1.3
1.
Data based on standard I2C protocol requirement, not tested in production.
2.
Cb = total capacitance of one bus line, in pF.
b.
Measurement points are done at 0.2Vdd_IO and 0.8Vdd_IO, for both port.
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