參數(shù)資料
型號(hào)： LSM303DLHTR
廠商： STMICROELECTRONICS
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PBGA28
封裝： 5 X 5 MM, 1 MM HEIGHT, ROHS COMPLIANT, PLASTIC, LGA-16
文件頁(yè)數(shù)： 17/47頁(yè)
文件大?。?/td> 585K
代理商： LSM303DLHTR
Digital interfaces
LSM303DLH
24/47
Doc ID 16941 Rev 1
7.1.1
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the 8th bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the LSM303DLH behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent. Once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the
7 LSb represent the actual register address while the MSB enables address auto-increment.
If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically increased to
allow multiple data read/write.
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit
(MSb) first. If a receiver cannot receive another complete byte of data until it has performed
some other function, it can hold the clock line SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to
receive because it is performing a real-time function) the data line must be left HIGH by the
slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
Table 11.
Transfer when master is writing one byte to slave
Master
ST
SAD + W
SUB
DATA
SP
Slave
SAK
Table 12.
Transfer when master is writing multiple bytes to slave
Master
ST
SAD + W
SUB
DATA
SP
Slave
SAK
Table 13.
Transfer when master is receiving (reading) one byte of data from slave
Master
ST
SAD + W
SUB
SR
SAD + R
NMAK
SP
Slave
SAK
DATA
相關(guān)PDF資料
PDF描述
LSM330DL SPECIALTY ANALOG CIRCUIT, PBGA28
LSN-0.75/16-D12HJ-C 1-OUTPUT 12.8 W DC-DC REG PWR SUPPLY MODULE
LSN-1.8/16-D12HJ-C 1-OUTPUT 28.8 W DC-DC REG PWR SUPPLY MODULE
LSN-1.2/16-D12HJ-C 1-OUTPUT 19.2 W DC-DC REG PWR SUPPLY MODULE
LSN-2.5/16-D12HJ-C 1-OUTPUT 40 W DC-DC REG PWR SUPPLY MODULE
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