參數(shù)資料
型號(hào)： LSM303DLHTR
廠商： STMICROELECTRONICS
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PBGA28
封裝： 5 X 5 MM, 1 MM HEIGHT, ROHS COMPLIANT, PLASTIC, LGA-16
文件頁(yè)數(shù)： 25/47頁(yè)
文件大?。?/td> 585K
代理商： LSM303DLHTR
LSM303DLH
Registers description
Doc ID 16941 Rev 1
31/47
internal registers related to trimming functions to permit good device behavior. If, for any
reason, the content of the trimming registers was changed, it is sufficient to use this bit to
restore the correct values. When the BOOT bit is set to ‘1’ the content of internal Flash is
copied to the corresponding internal registers and is used to calibrate the device. These
values are factory-trimmed and are different for every accelerometer. They permit good
device behavior and normally do not have to be modified. At the end of the boot process, the
BOOT bit is again set to ‘0’.
HPCF[1:0]. These bits are used to configure the high-pass filter cut-off frequency ft,which is
given by:
The equation can be simplified to the following approximated equation:
9.1.3
CTRL_REG3_A (22h)
Table 24.
High-pass filter mode configuration
HPM1
HPM0
High-pass filter mode
0
Normal mode (reset reading HP_RESET_FILTER)
0
1
Reference signal for filtering
1
0
Normal mode (reset reading HP_RESET_FILTER)
Table 25.
High-pass filter cut-off frequency configuration
HPcoeff2,1
ft [Hz]
Data rate = 50 Hz
ft [Hz]
Data rate = 100 Hz
ft [Hz]
Data rate = 400 Hz
ft [Hz]
Data rate = 1000 Hz
00
1
2
8
20
01
0.5
1
4
10
0.25
0.5
2
5
11
0.125
0.25
1
2.5
f
t
1
HPc
------------
–
f
s
2
π
------
ln
=
f
t
f
s
6HPc
----------------------
=
Table 26.
CTRL_REG3_A register
IHL
PP_OD
LIR2
I2_CFG1
I2_CFG0
LIR1
I1_CFG1
I1_CFG0
相關(guān)PDF資料
PDF描述
LSM330DL SPECIALTY ANALOG CIRCUIT, PBGA28
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