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參數(shù)資料
| 型號： | LSM303DLHTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA28 |
| 封裝： | 5 X 5 MM, 1 MM HEIGHT, ROHS COMPLIANT, PLASTIC, LGA-16 |
| 文件頁數(shù)： | 22/47頁 |
| 文件大小： | 585K |
| 代理商： | LSM303DLHTR |
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LSM303DLH
Registers description
Doc ID 16941 Rev 1
29/47
9
Registers description
The device contains a set of registers which are used to control its behavior and to retrieve
acceleration data. The register address, composed of 7 bits, is used to identify them and to
write the data through the serial interface.
9.1
Linear acceleration register
For linear acceleration sensors, the default (factory) 7-bit slave address is 001100xb.
9.1.1
CTRL_REG1_A (20h)
PM bits allow selection between power-down and two operating active modes. The device is
in power-down mode when the PD bits are set to “000” (default value after boot). Table 20
shows all the possible power mode configurations and respective output data rates. Output
data in the low-power modes are computed with a low-pass filter cut-off frequency defined
by DR1, DR0 bits.
DR bits, in the normal-mode operation, select the data rate at which acceleration samples
are produced. In low-power mode they define the output data resolution. Table 21 shows all
the possible configurations for the DR1 and DR0 bits.
Table 18.
CTRL_REG1_A register
PM2
PM1
PM0
DR1
DR0
Zen
Yen
Xen
Table 19.
CTRL_REG1_A description
PM2 - PM0
Power mode selection. Default value: 000
(000: Power-down; Others: refer to
DR1, DR0
Data rate selection. Default value: 00
(00:50 Hz; others: refer to
Zen
Z axis enable. Default value: 1
(0: Z axis disabled; 1: Z axis enabled)
Yen
Y axis enable. Default value: 1
(0: Y axis disabled; 1: Y axis enabled)
Xen
X axis enable. Default value: 1
(0: X axis disabled; 1: X axis enabled)
Table 20.
Power mode and low-power output data rate configurations
PM2
PM1
PM0
Power mode selection
Output data rate [Hz]
ODRLP
0
Power-down
--
0
1
Normal mode
ODR
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