參數(shù)資料
型號： LH79524N0F100A1
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： System-on-Chip
封裝： LH79524N0F100A1<SOT1019-1 (LFBGA208)|<<http://www.nxp.com/packages/SOT1019-1.html<1<Always Pb-free,;LH79525N0Q100A1<SOT1017-1 (LQFP176)|<<http://www.nxp.com/packages/SOT1
文件頁數(shù)： 37/64頁
文件大?。?/td> 970K
代理商： LH79524N0F100A1
System-on-Chip
LH79524/LH79525
Preliminary data sheet
Rev. 01
—
16 July 2007
37
NXP Semiconductors
NOTES:
1. The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter, power rail noise, and I/O conditioning will cause
these timings to vary nominally. It is recommended that designers add a small margin to avoid possible corner-case conditions.
2. The Write Wait States register (SWAITWRx) must be set to a minimum value of 3.
3. For each rising clock edge (HCLK) that the assertion of nWAIT lags the assertion of nCSx, another write wait state (SWAITRDx) must be
added to the minimum requirement.
4. nWAIT delay cycles are
not
added for all nWAIT assertions sampled prior to WST-3. These nWAIT assertions are ignored.
5. nWAIT delay cycles are added for all nWAIT assertions sampled from WST-3 until the de-assertion of nWAIT. nWAIT delay cycles are added
once the wait state countdown has reached WST-1.
6. Once nWAIT is sampled high, the current memory transaction is queued to complete.
7. Since static and dynamic memory cannot be accessed at the same time, any prolonged access (either due to nWAIT or the Extended Wait
Register) that causes an SDRAM refresh failure may cause SDRAM data to be lost.
8. Timing assumes Write Enable Delay register (SWAITWENx) is programmed to 0.
Figure 14. nWAIT Write Sequence (SWAITWRx = 3)
Table 17. nWAIT Write Sequence Parameter Definitions
PARAMETER
DESCRIPTION
MIN.
MAX.
UNIT
1
tIDA_nCS(x)_nWAIT
Delay from nCS(x) assertion to nWAIT assertion
0
16,365
HCLK periods
tDD_nWAIT_nCS(x)
Delay from nWAIT deassertion to nCS(x) deassertion
6
HCLK periods
tDD_nWAIT_nWE
Delay from nWAIT deassertion to nWE deassertion
5
HCLK periods
tA_nWAIT
Assertion time of nWAIT
2
HCLK periods
tDA_nCS(x)_nWAIT
HCLK
nCS(x)
nWE
nWAIT
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
tA_nWAIT
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
tDD_nWAIT_nCS(x)
tDD_nWAIT_nWE
LH79525-136
WST-3
DELAY
WST-2
DELAY
WST-1
DELAY
SQ-4
nWAIT
DELAY
SQ-3
nWAIT
DELAY
SQ-2
nWAIT
DELAY
SQ-1
nWAIT
DELAY
SQ-0
nWAIT
DELAY
WST-0
DELAY
END
CYCLE
nWE
END
CYCLE
nCS(x)
Transaction
Sequence
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參數(shù)描述
LH79524N0F100A1,55 功能描述:ARM微控制器 - MCU LCD,USB,ETH’NET,MMU,ADC,BGA208 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LH79524N0F100A1,551 制造商:NXP Semiconductors 功能描述:
LH79524N0F100A1;55 功能描述:ARM微控制器 - MCU LCD USB ETH’NET MMU RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LH79524N0F100A1-S 功能描述:ARM微控制器 - MCU ARM7 LCD MMU ENET RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LH79525 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:System-on-Chip
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