參數(shù)資料
型號(hào)： LH79524N0F100A1
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： System-on-Chip
封裝： LH79524N0F100A1<SOT1019-1 (LFBGA208)|<<http://www.nxp.com/packages/SOT1019-1.html<1<Always Pb-free,;LH79525N0Q100A1<SOT1017-1 (LQFP176)|<<http://www.nxp.com/packages/SOT1
文件頁(yè)數(shù)： 28/64頁(yè)
文件大?。?/td> 970K
代理商： LH79524N0F100A1
LH79524/LH79525
System-on-Chip
28
Rev. 01
—
16 July 2007
Preliminary data sheet
NXP Semiconductors
Power Supply Sequencing
When the linear regulator is
not
enabled, NXP rec-
ommends that the 1.8 V power supply be energized
before the 3.3 V supply. If this is not possible, the 1.8 V
supply may not lag the 3.3 V supply by more than 100
μ
s. If longer delay time is needed, it is recommended
that the voltage difference between the two power sup-
plies be within 1.5 V during power supply ramp up. To
avoid a potential latchup condition, voltage should be
applied to input pins only after the device is powered-
on as described above.
DC/AC Specifications
Unless noted, all data provided are based on:
-40°C to +85°C (Industrial temperature range)
VDDC = 1.7 V to 1.9 V
VDD = 3.0 V to 3.6 V, VDDA = 1.7 V to 1.9 V.
DC SPECIFICATIONS
NOTES:
1. Table 2 details each pin’s buffer type.
2. Running Typical Application over operating range.
3. Current measured with CPU stopped and all peripherals enabled
Linear Regulator DC Characteristics.
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
CONDITIONS
VIH
VIL
VIT+
VIT-
VHYST
CMOS input HIGH voltage
CMOS input LOW voltage
Positive Input threshold voltage (Schmitt pins)
Negative Input threshold voltage (Schmitt pins)
Schmitt trigger hysteresis
Output drive (2 mA type)
Output drive (4 mA type)
Output drive (8 mA type)
Output drive (12 mA type)
Output drive (2 mA type)
Output drive (4 mA type)
Output drive (8 mA type)
Output drive (12 mA type)
2.0
5.5
0.8
V
V
V
V
V
V
V
V
V
V
V
V
V
CEN = 1
CEN = 1
CSEN = 1
CSEN = 1
CSEN = 1
IOH = -2 mA
IOH = -4 mA
IOH = -8 mA
IOH = -12 mA
IOL = 2 mA
IOL = 4 mA
IOL = 7 mA
IOH = 12 mA
VIN = VDD or GND (Calculate input
leakage current at desired VDD)
Note 2
Notes 2, 3
2.0
0.8
0.35
VOH
1
2.6
2.6
2.6
2.6
VOL
1
0.4
0.4
0.4
2.6
RIN
Input leakage pull-up/pull-down resistors
40
k
IACTIVE
ISTANDBY Standby current
ISLEEP
Sleep current
ISTOP1
Stop1 current
ISTOP2
Stop2 current
ISTOP2
Stop2 current
ISTOP2
Stop2 current
ISTOP2
Stop2 current
Active current
85
50
3.8
420
115
95
45
25
mA
mA
mA
μ
A
μ
A
μ
A
μ
A
μ
A
RTC ON, Linear Regulator ON
RTC OFF, Linear Regulator ON
RTC ON, Linear Regulator OFF
RTC OFF, Linear Regulator OFF
SYMBOL
PARAMETER
MIN. TYP.
MAX.
UNIT
IQUIESCENT
ISLEEPLR
IOLR
VOLR
Quiescent Current
Current with Linear Regulator disabled
Output Current Range
Output Voltage, Linear Regulator
75
8
μ
A
μ
A
mA
V
0.0
200
1.84
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