System-on-Chip
LH79524/LH79525
Preliminary data sheet
Rev. 01
—
16 July 2007
23
NXP Semiconductors
Universal Asynchronous Receiver
Transmitter (UART)
The LH79524/LH79525 incorporates three UARTs.
UART0, UART1, and UART2 offer similar functionality
to the industry-standard 16C550. They perform serial-
to-parallel conversion on data received from a periph-
eral device and parallel-to-serial conversion on data
transmitted to the UART. The CPU reads and writes
data and control status information through the AMBA
APB interface. The transmit and receive paths are buff-
ered with internal FIFO memories that support pro-
grammable-service 'trigger levels', and overrun
protection. These FIFO memories enable up to 32
characters to be stored independently in both transmit
and receive modes.
Programmable bits-per-character (5, 6, 7, or 8)
Optional nine-bit mode to tag and recognize
characters as either data or address
Nine-bit Transmit FIFO and 12-bit Receive FIFO
Programmable FIFO trigger points
DMA support for UART0
Programmable IrDA SIR input/output for each UART
Separate 16-byte transmit and receive FIFOs to
reduce CPU interrupts
Programmable FIFO disabling for 1-byte depth
Programmable baud rate generator
Independent masking of transmit FIFO, receive
FIFO, receive timeout and modem status interrupts
False start bit detection
Line break generation and detection
Fully-programmable serial interface characteristics:
– 5-, 6-, 7-, or 8-bit data word length
– Even-, odd-, or no-parity bit generation and
detection
– 1 or 2 stop bit generation
IrDA SIR Encode/Decode block, providing:
– Programmable use of IrDA SIR or UART input/
output
– Supports data rates up to 115.2 kbit/s half-duplex
– Programmable internal clock generator, allowing
division of the Reference clock in increments of 1
to 512 for low-power mode bit durations.
– Loopback for testing
Vectored Interrupt Controller (VIC)
The Vectored Interrupt Controller combines the
interrupt request signals from 20 internal and eight
external interrupt sources and applies them, after
masking and prioritization, to the IRQ and FIQ interrupt
inputs of the ARM7TDMI processor core.
The Interrupt Controller incorporates a hardware
interrupt vector logic with programmable priority for up
to 16 interrupt sources. This logic reduces the interrupt
response time for IRQ type interrupts compared to
solutions using software polling to determine the high-
est priority interrupt source. This significantly improves
the real-time capabilities of the LH79524/LH79525 in
embedded control applications.
20 internal and eight external interrupt sources
– Individually maskable
– Status accessible for software polling
IRQ interrupt vector logic for up to 16 channels with
programmable priorities
All of the interrupt channels, with the exception of the
Watchdog Timer interrupt, can be programmed to
generate:
– FIQ interrupt request
– Non-vectored IRQ interrupt request (software to
poll IRQ source)
– Vectored IRQ interrupt request (up to 16 chan-
nels total)
The Watchdog timer can only generate FIQ interrupt
requests
External interrupt inputs programmable
– Edge triggered or level triggered
– Rising edge/active HIGH or falling edge/active
LOW
The 32 interrupt channels are shown in Table 10.
Table 10. Interrupt Channels
CHANNEL
INTERRUPT SOURCE
0
WDT
1
Not Used
2
COMRX (used for debug)
3
COMTX (used for debug)
4
Counter/Timer0 Combined
5
Counter/Timer1 Combined
6
Counter/Timer2 Combined
7
External Interrupt 0
8
External Interrupt 1
9
External Interrupt 2
10
External Interrupt 3
11
External Interrupt 4
12
External Interrupt 5
13
External Interrupt 6
14
External Interrupt 7
15
RTC_ALARM
16
ACD TSIRQ Combined
17
ADC Brown Out INTR