參數(shù)資料
型號(hào): LH79520N0Q000B1
廠商: NXP Semiconductors N.V.
元件分類(lèi): 數(shù)學(xué)處理器
英文描述: System-on-Chip
封裝: LH79520N0Q000B1<SOT1017-1 (LQFP176)|<<http://www.nxp.com/packages/SOT1017-1.html<1<Always Pb-free,;
文件頁(yè)數(shù): 31/59頁(yè)
文件大?。?/td> 666K
代理商: LH79520N0Q000B1
System-on-Chip
LH79520
Preliminary data sheet
Rev. 01
16 July 2007
31
NXP Semiconductors
Static Memory Controller Waveforms
nWAIT INPUT
The Static Memory Controller (SMC) supports an
nWAIT input that can be used by an external device to
extend the wait time during a memory access. The
SMC samples nWAIT at the beginning of at the begin-
ning of each system clock cycle. The system clock
cycle in which the nCSx signal is asserted counts as
the first wait state. See Figure 11.
The SMC recognizes that nWAIT is active within 2
clock cycles after it has been asserted. To assure that
the current access (read or write) will be extended by
nWAIT, at least two wait states must be programmed
for this bank of memory. If N wait states are pro-
grammed, then the Static Memory Controller (SMC)
holds this state for N system clocks, or until the SMC
detects that nWAIT is inactive, whichever occurs last.
As the number of wait states programmed increases,
the amount of delay before nWAIT must be asserted
also increases. If only 2 wait states are programmed,
then nWAIT must be asserted in the clock cycle imme-
diately following the clock cycle during which the nCSx
signal is asserted. Once the SMC detects that the
external device has deactivated nWAIT, the SMC will
complete its access in 3 system clock cycles.
The formula for the allowable delay between assert-
ing nCSx and asserting nWAIT is:
tASSERT = (system clock period) × (Wait States - 1)
(where Wait States is from 2 to 31.)
READ AND WRITE WAVEFORMS
Figure 12 shows the waveform and timing for an
External Static Memory Write. Figure 13 shows the
waveform and timing for an External Static Memory
Read, with one Wait State. Figure 14 shows the wave-
form and timing for an External Static Memory Read,
with two Wait States.
The signal tIDD is shown without a setup time, as
measurements are made from the Address Valid point
and HCLK is an internal signal, shown for reference only.
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