參數(shù)資料
型號: LH79520N0Q000B1
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: System-on-Chip
封裝: LH79520N0Q000B1<SOT1017-1 (LQFP176)|<<http://www.nxp.com/packages/SOT1017-1.html<1<Always Pb-free,;
文件頁數(shù): 30/59頁
文件大小: 666K
代理商: LH79520N0Q000B1
LH79520
System-on-Chip
30
Rev. 01
16 July 2007
Preliminary data sheet
NXP Semiconductors
NOTES:
1. INTR[5:0] are asynchronous signals. Interrupts must be held Active until serviced in Level Sensitive Mode,
and held Active for a minimum of 20 ns in Edge Sensitive Mode.
2. nDACK0, DACK1 and DREQ[1:0] are asynchronous signals. They must be held Active until serviced,
for a minimum of 20 ns.
EXTERNAL CLOCKS
Table 12. External Clocks AC Specifications
NOTES:
1. PCLK is the period chosen for the internal peripheral
clock domain.
2. MAX. period is DC. See ‘Recommended Operating Conditions’.
nSDCS[1:0]
Output 30 pF
8 mA
tOVSC
tOHSC
tSDCLK
11 ns
SDCS Data Mask Valid
SDCS Data Mask Hold
SDRAM Clock Period
2 ns
SDCLK
Output 30 pF
8 mA
19.37 ns
SYNCHRONOUS SERIAL PORT (SSP)
SSPFRM
Output 50 pF
2 mA
tOVSSPFRM
14 ns
SSPFRM Output Valid,
Referenced to SSPCLK
SSPEN Output Valid,
Referenced to SSPCLK
SSP Transmit Valid
SSP Receive Setup
SSPEN
Output 50 pF
2 mA
tOVSSPENB
14ns
SSPTX
SSPRX
Output 50 pF
Input
2 mA
tOVSSPOUT
tISSSPIN
14ns
17 ns
INTERRUPTS
INTR[5:0]
Input
Note 1
Table 11. AC Signal Characteristics (Cont’d)(Industrial)
SIGNAL
TYPE LOAD DRIVE
SYMBOL
MIN.
MAX.
DESCRIPTION
SYMBOL
DESCRIPTION
MIN.
UNIT
tCLKIN
CLKIN Period
6.66
ns
tCLKINH
CLKIN HIGH Time
2.8
ns
tCLKINL
CLKIN LOW TIme
2.8
ns
tSSPCLK
SSPCLK Period
1
PCLK
tSSPCLKH
SSPCLK HIGH Time
0.4
PCLK
tSSPCLKL
SSPCLK LOW Time
0.4
PCLK
tUCLK
UCLK
1
PCLK
tUCLKH
UCLK HIGH Time
0.4
PCLK
tUCLKL
UCLK LOW Time
0.4
PCLK
Figure 8. External Clock AC Timing
tCLKINL
tCLKIN
tCLKINH
79520-57
Figure 9. Synchronous Serial I/F Clocks AC Timing
Figure 10. External UARTs/SIR Clock AC Timing
tSSPCLK
tSSPCLKL
79520-58
tSSPCLKH
79520-59
tUCLKH
tUCLK
tUCLKL
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