LH79520
System-on-Chip
18
Rev. 01
—
16 July 2007
Preliminary data sheet
NXP Semiconductors
Simultaneous servicing of up to 4 data streams
Three transfer modes are supported:
– Memory to Memory
– Peripheral to Memory
– Memory to Peripheral
Identical source and destination capabilities
Transfer Size Programmable (Byte, Half-word, Word)
Burst Size Programmable
Address Increment or Address Freeze
Transfer Error indication for each stream via an
interrupt
16-word FIFO array with pack and unpack logic
Handles all combinations of byte, half-word or word
transfers from input to output.
Color LCD Controller (CLCDC)
The CLCDC provides all the necessary control and
drive signals to interface directly with a variety of color
and monochrome LCD panels.
Supports single and dual scan color and mono-
chrome Super Twisted Nematic (STN) displays with
4- or 8-bit interfaces
Supports Thin Film Transistor (TFT) color displays
Programmable resolution up to 800 × 600
– 800 × 600 (16-bit color can only be supported at
≤
65 Hz refresh rates with 800 × 600 resolution).
15 gray-level mono, 3,375 color STN, and 64 k color
TFT support
1, 2, or 4 bits-per-pixel
(BPP) for monochrome STN
1-, 2-, 4-, or 8-BPP palettized color displays for color
STN and TFT
True-color non-palettized, for color STN and TFT
Programmable timing for different display panels
256-entry, 16-bit palette fast-access RAM
Frame, line and pixel clock signals
AC bias signal for STN or data enable signal for
TFT panels
Patented grayscale algorithm
Interrupt Generation Events
Dual 16-deep programmable 32-bit wide FIFOs for
buffering incoming data.
ADVANCED LCD INTERFACE
The Advanced LCD Interface peripheral allows for
direct connection to ultra-thin panels that do not include
a timing ASIC. It converts TFT signals from the Color
LCD controller to provide the proper signals, timing and
levels for direct connection to a panel’s Row and Col-
umn drivers for AD-TFT, HR-TFT, or any technology of
panel that allows for a connection of this type. The
Advanced LCD Interface peripheral also provides a
bypass mode that allows the LH79520 to interface to the
built-in timing ASIC in standard TFT and STN panels.
Synchronous Serial Port (SSP)
The SSP is a master-only interface for synchronous
serial communication with slave peripheral devices that
support protocols for Motorola SPI, National Semicon-
ductor MICROWIRE, or Texas Instruments Synchro-
nous Serial Interface.
Master-only operation
Programmable clock rate
Separate transmit FIFO and receive FIFO buffers,
16 bits wide, 8 locations deep
DMA for transmit and receive
Programmable interface protocols: Motorola SPI,
National Semiconductor MICROWIRE, or Texas
Instruments Synchronous Serial Port
Programmable data frame size from 4 to 16 bits
Independent masking of transmit FIFO, receive
FIFO and receive overrun interrupts
Available internal loopback test mode.
Universal Asynchronous
Receiver Transmitter (UART)
The LH79520 incorporates three UARTs.
Programmable use of UART0 or IrDA SIR input/output
Separate 16-byte transmit and receive FIFOs to
reduce CPU interrupts
Programmable FIFO disabling for 1-byte depth
Programmable baud rate generator
Independent masking of transmit FIFO, receive
FIFO, receive timeout and modem status interrupts
False start bit detection
Line Break generation and detection
Fully-programmable serial interface characteristics:
– 5-, 6-, 7-, or 8-bit data word length
– Even-, odd- or no-parity bit generation and detection
– 1 or 2 stop bit generation
IrDA SIR Encode/Decode block, providing:
– Programmable use of IrDA SIR or UART0
input/output
– Supports data rates up to 115.2 Kbps half-duplex
– Programmable internal clock generator, allowing
division of the Reference clock in increments of 1
to 512 for low-power mode bit durations.