參數(shù)資料
型號(hào)： LH75401N0Q100C0
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： System-on-Chip
封裝： LH75401N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LH75411N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1
文件頁數(shù)： 39/63頁
文件大?。?/td> 665K
代理商： LH75401N0Q100C0
System-on-Chip
LH75401/LH75411
Preliminary data sheet
Rev. 01
—
16 July 2007
39
NXP Semiconductors
POWER SUPPLY SEQUENCING
When using an external 1.8 V supply (instead of the
internal 1.8 V regulator), the external 1.8 V power sup-
ply must be energized before the 3.3 V supply. Other-
wise, the 1.8 V supply may not lag the 3.3 V supply by
more than 10 μs.
If a longer delay time is needed, the voltage differ-
ence between the two power supplies must be within
1.5 V during power supply ramp up.
To avoid a potential latchup condition, voltage
should be applied to input pins only after the device is
powered-on as described above.
LINEAR REGULATOR
Although this device contains an on-board regulator,
using its output to power external devices is not recom-
mended. External loads can affect the regulator’s sta-
bility and introduce noise into the supply. NXP cannot
guarantee device performance at rated speeds and
temperatures with external loads connected to this
supply.
CURRENT CONSUMPTION BY OPERATING MODE
Current consumption can depend on a number of
parameters. To make this data more usable, the values
presented in Table 22 were derived under the condi-
tions presented here.
Maximum Specified Value
The values specified in the MAXIMUM column were
determined using these operating characteristics:
All IP blocks either operating or enabled at maximum
frequency and size configuration
Core operating at maximum power configuration
All I/O loads at maximum (50 pF)
All voltages at maximum specified values
Maximum specified ambient temperature.
Typical
The values in the TYPICAL column were determined
using a ‘typical’ application under ‘typical’ environmental
conditions and the following operating characteristics:
SPI, Timer, and UART peripherals operating; all
other peripherals disabled
LCD enabled with 320 × 240 × 16-bit color, 60 Hz
refresh rate
I/O loads at nominal
FCLK = 51.6 MHz; HCLK = 51.6 MHz
All voltages at typical values
Nominal case temperature.
PERIPHERAL CURRENT CONSUMPTION
In addition to the modal current consumption, Table
23 shows the typical current consumption for each of
the on-board peripheral blocks. The values were deter-
mined with the peripheral clock running at maximum
frequency, typical conditions, and no I/O loads. This
current is supplied by the 1.8 V power supply.
NOTES:
1. ICHIP = Chip Current with Linear Regulator (Core + I/O)
2. ICORE, IIO, IANALOG are the respective current consumption
specifications for VDDC, VDD, and VDDA.
Table 22. Current Consumption by Mode
SYMBOL
PARAMETER
TYP. UNITS
ACTIVE MODE
ICHIP
Chip Current with Linear Regulator
50.2
mA
ICORE
Core Current without Linear Regulator
42.1
mA
IIO
I/O Current without Linear Regulator
5
mA
IANALOG Analog Current
1.3
mA
STANDBY MODE (TYPICAL CONDITIONS ONLY)
ICHIP
Core Current with Linear Regulator
42.7
mA
ICORE
Core Current without Linear Regulator
34.6
mA
IIO
Current drawn by I/O
0.8
mA
IANALOG Analog Current
1.3
mA
SLEEP MODE (TYPICAL CONDITIONS ONLY)
ICHIP
Core Current with Linear Regulator
3.9
mA
ICORE
Core Current without Linear Regulator
2.5
mA
IIO
Current drawn by I/O
400
μA
IANALOG Analog Current
1.2
mA
STOP1 MODE
ISTOP
Core Current with Linear Regulator, I/O,
and 14.7456 MHz osc.
2.96
mA
STOP2 MODE (RTC ON)
ILEAK
Leakage Current, Core and I/O
34
μA
STOP2 MODE (RTC OFF)
ILEAK
Leakage Current, Core and I/O
18
μA
Table 23. Peripheral Current Consumption
PERIPHERAL
TYPICAL
UNITS
UARTs
200
μA
RTC
5
μA
DMA
4.1
mA
SSP
500
μA
Counter/Timers
200
μA
LCD
2.2
mA
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