參數(shù)資料
型號(hào)： LH75401N0Q100C0
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： System-on-Chip
封裝： LH75401N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LH75411N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1
文件頁(yè)數(shù)： 29/63頁(yè)
文件大?。?/td> 665K
代理商： LH75401N0Q100C0
System-on-Chip
LH75401/LH75411
Preliminary data sheet
Rev. 01
—
16 July 2007
29
NXP Semiconductors
CAN 2.0B FEATURES
Full compliance with 2.0A and 2.0B Bosch
specifications
Supports 11-bit and 29-bit identifiers
Supports bit rates up to 1Mbit/s
64-byte receive FIFO
Software-driven bit-rate detection for hot plug-in
support
Single-shot transmission option
Acceptance filtering
Listen Only Mode
Reception of ‘own’ messages
Error interrupt generated for each CAN bus error
Arbitration-lost interrupt with record of bit position
Read/write error counters
Last error register
Programmable error-limit warning.
Analog-to-Digital Converter (ADC)/
Brownout Detector
The ADC is an AMBA-compliant peripheral that con-
nects as a slave to the APB. The ADC block consists of
an 8-channel, 10-bit Analog-to-Digital Converter with
integrated Touch Screen Controller. The complete
Touch Screen interface is achieved by combining the
front-end biasing, control circuitry with analog-to-digital
conversion, reference generation, and digital control.
The ADC also has a programmable measurement
clock derived from the system clock. The clock drives
the measurement sequencer and the successive-
approximation circuitry.
The ADC includes a Brownout Detector. The Brown-
out Detector is an asynchronous comparator that com-
pares a divided version of the 3.3 V supply and a
bandgap-derived reference voltage. If the supply dips
below a Trip point, the Brownout Detector sets a status
register bit. The status bit is wired to the VIC and can
interrupt the processor core. This allows the Host Con-
troller to warn users of an impending shutdown and may
provide the ADC with sufficient time to save its state.
ADC/BROWNOUT DETECTOR FEATURES
10-bit fully differential Successive Approximation
Register (SAR) with integrated sample/hold
8-channel multiplexer for routing user-selected inputs
to the ADC in Single Ended and Differential Modes
16-entry × 16-bit-wide FIFO that holds the 10-bit
ADC output and a 4-bit tag number
Front bias-and-control network for Touch Screen
interface and support functions compatible with indus-
try-standard 4- and 5-wire touch-sensitive panels
Touch-pressure sensing circuits
Pen-down sensing circuit and interrupt generator
Voltage-reference generator that is independently
controlled
Conversion automation function to minimize control-
ler interrupt overhead
Brownout Detector.
Synchronous Serial Port (SSP)
The SSP is a master-only interface for synchronous
serial communication with slave peripheral devices that
have a Motorola SPI, National Semiconductor
Microwire, or Texas Instruments DSP-compatible
Synchronous Serial Interface (SSI).
The SSP performs serial-to-parallel conversion on
data received from a peripheral device. The transmit and
receive paths are buffered with internal FIFO memories.
These memories store eight 16-bit values independently
in both transmit and receive modes. During transmission:
Data writes to the transmit FIFO via the APB
interface.
The transmit data is queued for parallel-to-serial
conversion onto the transmit interface.
The transmit logic formats the data into the appropri-
ate frame type:
– Motorola SPI
– National Semiconductor Microwire
– Texas Instruments DSP-compatible SSI.
SSP FEATURES
SSI in Master Only Mode. The SSP performs serial
communications as a master device in one of three
modes:
– Motorola SPI
– Texas Instruments DSP-compatible synchronous
serial interface
– National Semiconductor Microwire.
Two 16-bit-wide, 8-entry-deep FIFOs, one for data
transmission and one for data reception.
Supports interrupt-driven data transfers that are
greater than the FIFO watermark.
Programmable clock bit rate.
Programmable data frame size, from 4 to 16 bits long,
depending on the size of data programmed. Each
frame transmits starting with the most-significant bit.
Four interrupts, each of which can be individually
enabled or disabled using the SSP Control Register
bits. A combined interrupt is also generated as an
OR function of the individual interrupt requests.
Loopback Test Mode.
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