參數(shù)資料
型號: LH75401N0Q100C0
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: System-on-Chip
封裝: LH75401N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LH75411N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1
文件頁數(shù): 32/63頁
文件大小: 665K
代理商: LH75401N0Q100C0
LH75401/LH75411
System-on-Chip
32
Rev. 01
16 July 2007
Preliminary data sheet
NXP Semiconductors
Reset, Clock, and Power Controller (RCPC)
The RCPC lets users control System Reset, clocks,
power management, and external interrupt condition-
ing via the AMBA APB interface. This control includes:
Enabling and disabling various clocks
Managing power-down sequencing
Selecting the sources for various clocks.
The RCPC provides for an orderly start-up until the
crystal oscillator stabilizes and the PLL acquires lock. If
users want to change the system clock frequency dur-
ing normal operation, the RCPC ensures a seamless
transition between the old and new frequencies.
RCPC FEATURES
Manages five Power Modes for minimizing power
consumption: Active, Standby, Sleep, Stop1, and
Stop2
Generates the system clock (HCLK) from either the
PLL clock or the PLL-bypassed (oscillator) clock,
divided by 2, 4, 6, 8, … 30
Generates three UART clocks from oscillator clock
Generates the 1 Hz RTC clock
Generates the SSP and LCD clocks from HCLK,
divided by 1, 2, 4, 8, 16, 32, or 64
Provides a selectable external clock output
Generates system and RTC Resets based on an
external reset, Watchdog Timer reset, or soft reset
Configures seven HIGH/LOW-level or rising/falling
edge-trigger external interrupts and converts them to
HIGH-level trigger interrupt outputs required by the VIC
Generates remap outputs used by the memory map
decoder
Provides an identification register
Supports external or watchdog reset status.
Operating Modes
The LH75401/LH75411 microcontrollers support
three operating modes:
Normal Mode
PLL Bypass Mode, where the internal PLL is
bypassed and an external clock source is used; oth-
erwise the chip operates normally
EmbeddedICE Mode, where the JTAG port
accesses the TAP Controller in the core and the core
is placed in Debug Mode.
The state of the TEST1, TEST2, and nRESETIN sig-
nals determines the operating mode entered at Power-
on Reset (see Table 12).
NOTE:
TEST1, TEST2, and nRESETIN are latched on the rising
edge of nPOR. The microcontroller stays in that operating
mode until power is removed or nPOR transitions from LOW
to HIGH.
General Purpose Input/Output (GPIO)
The LH75401/LH75411 microcontrollers have 10
GPIO ports:
Seven 8-bit ports
Two 7-bit ports
One 6-bit port.
The GPIO ports are designated A through J and pro-
vide 76 bits of programmable input/output (see Table
13). Pins of all ports, except Port J, can be configured
as inputs or outputs. Port J is input only. Upon System
Reset, all ports default to inputs.
Table 12. Device Operating Modes
OPERATING MODE
TEST2
TEST1
nRESETIN
Reserved
0
0
0
PLL Bypass
0
0
1
Reserved
0
1
x
Reserved
1
0
0
EmbeddedICE
1
0
1
Normal
1
1
x
Table 13. GPIO Ports
PORT
PROGRAMMABLE PINS
A
8 Input/Output Pins
B
6 Input/Output Pins
C
8 Input/Output Pins
D
7 Input/Output Pins
E
8 Input/Output Pins
F
7 Input/Output Pins
G
8 Input/Output Pins
H
8 Input/Output Pins
I
8 Input/Output Pins
J
8 Input Pins
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