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參數(shù)資料
| 型號： | LH75401N0Q100C0 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | System-on-Chip |
| 封裝： | LH75401N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LH75411N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1 |
| 文件頁數(shù)： | 28/63頁 |
| 文件大?。?/td> | 665K |
| 代理商： | LH75401N0Q100C0 |
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LH75401/LH75411
System-on-Chip
28
Rev. 01
—
16 July 2007
Preliminary data sheet
NXP Semiconductors
UART 2 FEATURES
Similar functionality to the industry-standard 82510
Supported baud rates up to 3,225,600 baud (given a
system clock of 51.6096 MHz)
5, 6, 7, 8, or 9 data bits per character
Even, odd, HIGH, LOW, software, or no parity-bit
generation and detection
3/4, 1, 1-1/4, 1-1/2, 1-3/4, or 2 stop-bit generation
μ
LAN address flag
Full-duplex operation
Separate transmit and receive FIFOs, with program-
mable depth (1 or 4). Each FIFO has overrun protec-
tion and:
– Programmable receive trigger levels: 1/4, 1/2,
3/4, or full
– Programmable transmit trigger levels: empty, 1/4,
1/2, 3/4.
Two 16-bit baud-rate generators.
One interrupt that can be triggered by transmit and
receive FIFO thresholds, receive errors, control
character or address marker reception, or timer
timeout
Generation and detection of breaks during UART
transactions
Support for local loopback, remote loopback, and
auto-echo modes
μ
LAN Address Mode.
Timers
The LH75401/LH75411 microcontrollers have three
16-bit timers. The timers are clocked by the system
clock, but have an internal scaled-down system clock
that is used for the Pulse Width Modulator (PWM) and
compare functions.
All counters are incremented by an internal pre-
scaled counter clock or external clock and can gener-
ate an overflow interrupt. All three timers have separate
internal prescaled counter clocks, with either a com-
mon external clock or a prescaled version of the sys-
tem clock.
Timer 0 has five Capture Registers and two Com-
pare Registers.
Timer 1 and Timer 2 have two Capture and two Com-
pare Registers each.
The Capture Registers have edge-selectable inputs
and can generate an interrupt. The Compare Registers
can force the compare output pin either HIGH or LOW
upon a match.
The timers support a PWM Mode that uses the two
Timer Compare Registers associated with a timer to
create a PWM. Each timer can generate a separate
interrupt. The interrupt becomes active if any enabled
compare, capture, or overflow interrupt condition
occurs. The interrupt remains active until all compare,
capture, and overflow interrupts are cleared.
Real Time Clock (RTC)
The RTC is an AMBA slave module that connects to
the APB. The RTC provides basic alarm functions or
acts as a long-time base counter by generating an inter-
rupt signal after counting for a programmed number of
cycles of an RTC input. Counting in 1-second intervals
is achieved using a 1 Hz clock input to the RTC.
RTC FEATURES
32-bit up-counter with programmable load
Programmable 32-bit match Compare Register
Software-maskable interrupt that is set when the
Counter and Compare Registers have identical values.
Controller Area Network (CAN)
The CAN 2.0B Controller is an AMBA-compliant
peripheral that connects as a slave to the APB. The
CAN Controller is located between the processor core
and a CAN Transceiver, and is accessed through the
AMBA port.
CAN communications are performed serially, at a
maximum frequency of 1 MB/s, using the TX (transmit)
and RX (receive) lines. The TX and RX signals for data
transmission and reception provide the communications
interface between the CAN Controller and the CAN bus.
All peripherals share the TX and RX lines, and always
see the common incoming and outgoing data.
Bus arbitration follows the CAN 2.0A and CAN 2.0B
specifications. The bus is always controlled by the
node with the highest priority (lowest ID). Only after the
bus has been released can the next highest priority
node control it. Transmit and receive errors are han-
dled according to the CAN protocol.
Bus timing is critical to the CAN protocol. Therefore,
the CAN Controller has two programmable Bus Timing
Registers that define timing parameters.
NOTE:
The CAN Controller pertains to the LH75401 microcontrol-
lers.
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相關(guān)代理商/技術(shù)參數(shù) |
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| LH75401N0Q100C0,55 | 功能描述:ARM微控制器 - MCU ARM7 CAN LCD ADC RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LH75401N0Q100C055 | 制造商:NXP Semiconductors 功能描述:MCU ARM7 BLUESTREAK 144LQFP |
| LH75401N0Q100C055 | 制造商:NXP Semiconductors 功能描述:IC 32BIT MCU 84MHZ LQFP-144 |
| LH75401N0Q100C0551 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| LH75401N0Q100C0-S | 制造商:NXP Semiconductors 功能描述:SOC Microcontroller 1.98V 144-Pin LQFP Tray |
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