參數(shù)資料
型號(hào): LFXP15C-4FN256C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
中文描述: FPGA, 1932 CLBS, PBGA256
封裝: 17 X 17 MM, LEAD FREE, FPBGA-256
文件頁數(shù): 67/130頁
文件大?。?/td> 1312K
代理商: LFXP15C-4FN256C
3-10
DC and Switching Characteristics
Lattice Semiconductor
LatticeXP Family Data Sheet
Differential HSTL and SSTL
Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-
able single-ended output classes (class I and class II) are supported in this mode.
LVDS25E
The top and bottom side of LatticeXP devices support LVDS outputs via emulated complementary LVCMOS out-
puts in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possi-
ble solution for point-to-point signals.
Figure 3-1. LVDS25E Output Termination Example
Table 3-1. LVDS25E DC Conditions
Over Recommended Operating Conditions
BLVDS
The LatticeXP devices support BLVDS standard. This standard is emulated using complementary LVCMOS out-
puts in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-
drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible
solution for bi-directional multi-point differential signals.
Parameter
Description
Typical
Units
VOH
Output high voltage
1.43
V
VOL
Output low voltage
1.07
V
VOD
Output differential voltage
0.35
V
VCM
Output common mode voltage
1.25
V
ZBACK
Back impedance
100
ohms
IDC
DC output current
3.66
mA
+
-
Bourns
CAT16-LV4F12
RS=165 ohms
(±1%)
RS=165 ohms
(±1%)
RD = 140 ohms
(±1%)
RD = 100 ohms
(±1%)
OFF-chip
Transmission line, Zo = 100 ohm differential
VCCIO = 2.5V (±5%)
ON-chip
OFF-chip
ON-chip
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