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參數(shù)資料
| 型號(hào)： | LC6529F |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 4-Bit Microcomputer for Small-Scale Control Applications |
| 中文描述： | 4小位微機(jī)控制應(yīng)用規(guī)模 |
| 文件頁(yè)數(shù)： | 9/39頁(yè) |
| 文件大?。?/td> | 525K |
| 代理商： | LC6529F |
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Specifications
LC6529N
Absolute Maximum Ratings
at Ta = 25°C, V
SS
= 0 V
Note: 1. When the oscillator circuit in Figure 3 and the guaranteed constant are used, this is guaranteed over the full amplitude.
2. Averaged over 100-ms interval.
Allowable Operating Ranges
at Ta = –40 to +85°C, V
SS
= 0 V, V
DD
= 3.0 to 6.0 V
Note:
*
Maintain the power supply voltage at V
DD
until the HALT instruction has completed execution, placing the chip in the standby mode. Block
chattering from entering PA3 during the HALT instruction execution cycle.
No. 5117-9/39
LC6529N, LC6529F, LC6529L
Parameter
Symbol
Conditions
min
typ
max
Unit
Maximum supply voltage
V
DD
max
V
I
1
V
I
2
V
I
3
V
O
V
IO
1
V
IO
2
I
OP
I
OA
Σ
I
OA
1
V
DD
OSC1
*
1
–0.3
+7.0
V
–0.3
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
Input voltage
TEST, RES
–0.3
V
Port E (PE) configuration
–0.3
Output voltage
OSC2
Voltages up to that generated allowed.
V
I/O voltages
Open-drain (OD) configuration
–0.3
+15
V
Pull-up (PU) resistor configuration
–0.3
V
DD
+ 0.3
Peak output current
PA, PC, PD
–2
+20
mA
PA, PC, PD: Average for pin over 100-ms interval
PA: Total current for pins PA0 to PA3
*
2
–2
+20
Average output current
–6
+40
mA
Σ
I
OA
2
PC, PD: Total current for pins PC0 to PC3 and
PD0 to PD3
*
2
–14
+90
Pd max1
Ta = –40 to +85°C (DIP24S)
360
Allowable power dissipation
Pd max2
Ta = –40 to +85°C (SSOP24)
165
mW
Pd max3
Ta = –40 to +85°C (MFP30S)
150
Operating temperature
Topr
–40
+85
°C
Storage temperature
Tstg
–55
+125
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply voltage
V
DD
V
ST
V
DD
V
DD
: Preserves contents of RAM and registers
*
.
Open-drain (OD) configuration: With output N-channel
transistor off
3.0
6.0
V
Standby voltage
1.8
6.0
V
V
IH
1
0.7 V
DD
13.5
V
IH
2
Pull-up (PU) resistor configuration: With output
N-channel transistor off
0.7 V
DD
V
DD
Input high level voltage
V
V
IH
3
V
IH
4
V
IH
5
PE: Using port E configuration
0.7 V
DD
0.8 V
DD
0.8 V
DD
V
DD
V
DD
V
DD
RES: V
DD
= 1.8 to 6 V
OSC1: Using external clock option
V
IL
1
PA, PC, PD: With output N-channel transistor off,
V
DD
= 4 to 6 V
PA, PC, PD: With output N-channel transistor off
V
SS
0.3 V
DD
V
IL
2
V
IL
3
V
IL
4
V
IL
5
V
IL
6
V
IL
7
V
IL
8
V
IL
9
V
IL
10
fop
(Tcyc)
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
0.25 V
DD
0.3 V
DD
0.25 V
DD
0.25 V
DD
0.2 V
DD
0.3 V
DD
0.25 V
DD
0.25 V
DD
0.2 V
DD
PE: Using port E configuration, V
DD
= 4 to 6 V
PE: Using port E configuration
Input low level voltage
OSC1: Using external clock option, V
DD
= 4 to 6 V
OSC1: Using external clock option
V
TEST: V
DD
= 4 to 6 V
TEST
RES: V
DD
= 4 to 6 V
RES
Operating frequency
(cycle time)
Using the built-in 1/3 or 1/4 frequency dividers extends
the maximum to 4.33 MHz.
200 (20)
1444 (2.77) kHz (μs)
Continued on next page.
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