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| 型號(hào)： | LC6529F |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 4-Bit Microcomputer for Small-Scale Control Applications |
| 中文描述： | 4小位微機(jī)控制應(yīng)用規(guī)模 |
| 文件頁(yè)數(shù)： | 16/39頁(yè) |
| 文件大?。?/td> | 525K |
| 代理商： | LC6529F |
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Electrical Characteristics
at Ta = –40 to +85°C, V
SS
= 0 V, V
DD
= 3.0 to 6.0 V
Note:
*
The RC oscillator and external clock options require a Schmidt trigger configuration for OSC1.
Note:
*
f
CFOSC
is the allowable oscillator frequency.
No. 5117-16/39
LC6529N, LC6529F, LC6529L
Parameter
Symbol
Conditions
min
typ
max
Unit
Open-drain (OD) configuration for port: With output
N-channel transistor off. (Includes transistor’s leak
current.) V
IN
= 13.5 V
PE: Using port E configuration, V
IN
= V
DD
OSC1: Using external clock option, V
IN
= V
DD
Open-drain (OD) configuration for port: With output
N-channel transistor off. (Includes transistor’s leak
current.) V
IN
= V
SS
Pull-up (PU) resistor configuration for port:
With output N-channel transistor off. (Includes
transistor’s leak current.) V
IN
= V
SS
Pull-up (PU) resistor configuration for port C:
With output N-channel transistor off. (Includes
transistor’s leak current.) V
IN
= V
SS
PE: Using port E configuration, V
IN
= V
SS
RES: V
IN
= V
SS
OSC1: Using external clock option, V
IN
= V
SS
Pull-up (PU) resistor configuration for port C:
I
OH
= –300 μA, V
DD
= 4 to 6 V
Pull-up (PU) resistor configuration for port C:
I
OH
= –60 μA
PA, PC, PD: I
OL
= 10 mA, V
DD
= 4 to 6 V
PA, PC, PD: With I
OL
for each port less than or equal
to 1 mA, I
OL
= 1.8 mA
RES
I
IH
1
5.0
Input high level current
μA
I
IH
2
I
IH
3
1.0
1.0
I
IL
1
–1.0
μA
I
IL
2
–220
–71.5
Input low level current
I
IL
3
–6.00
–2.17
mA
I
IL
4
I
IL
5
I
IL
6
–1.0
–45
–10
μA
–1.0
V
OH
1
V
DD
– 1.2
Output high level voltage
V
V
OH
2
V
DD
– 0.5
V
OL
1
1.5
Output low level voltage
V
OL
2
0.4
V
Hysteresis voltage
V
HIS
1
V
HIS
2
0.1 V
DD
0.1 V
DD
V
OSC1
*
: Using RC oscillator or external clock option
Parameter
Symbol
Conditions
min
typ
max
Unit
[Current drain]
Ceramic oscillator
I
DD OP
1
V
DD
: Figure 2, 4 MHz, 200 to 4330 kHz,
1/1 frequency divider
Note: With output N-channel transistor off and
port level = V
DD
V
DD
: With output N-channel transistor off and
port level = V
DD
, V
DD
= 6 V
V
DD
: With output N-channel transistor off and
port level = V
DD
, V
DD
= 3 V
1.6
4.0
mA
External clock
I
DD OP
2
1.6
4.2
I
DD st
1
0.05
10
Standby operation
μA
I
DD st
2
0.025
5
[Oscillator characteristics] (Ceramic oscillator)
Oscillator frequency
f
CFOSC
t
CFS
OSC1, OSC2: Figure 2, f
O
= 4 MHz
*
Figure 3, f
O
= 4 MHz
3840
4000
4160
kHz
Oscillator stabilization interval
10
ms
[Pull-up resistors]
Pull-up (PU) resistor configuration for port A or D:
With output N-channel transistor off and V
IN
= V
SS
,
V
DD
= 5 V
Pull-up (PU) resistor configuration for port C:
With output N-channel transistor off and V
IN
= V
SS
,
V
DD
= 5 V
RES: V
IN
= V
SS
, V
DD
= 5 V
RPP1
30
70
130
I/O ports
k
RPP2
1.0
2.3
3.9
Reset port
Ru
200
500
725
External reset characteristic:
Reset time
t
RST
See
Figure 5.
Pin capacitance
C
P
f = 1 MHz, V
IN
= V
SS
for pins other than one
being measured
10
pF
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