
register
44 Wed May 28 17:37:25 1997
Draft 1/21/97
4-44
Registers
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
4.8.14
Frequency
Synthesizer Cell
(FSC) Clock
Divide Value
Register
This 16-bit write-only register is used to write clock divide values. Bit 1
of the System Mode Register is used to indicated which value is written.
When the System Mode register value is 1, DCO_DIV is written; if the
4.9
L64007’s
Parallel Port
Interface to the
L64002
(Group 6)
Address space 0xFFFF8 - 0xFFFFF is used to access the L64002 A/V
decoder through the L64007 device. When the L64007 Mode Register bit
AV_S/P is 1, the A/V channel control lines and the AUXD[7:0] lines are
used to communicate with the L64002 in parallel conguration. The par-
allel port can be used to transfer audio and video PES data streams from
the on-chip transport buffers to the L64002. This port also can transfer
initialization and status data to the host processor. The arbitration
between channel data and host data transfer is implemented in the chip.
The AV_CS signal is sent to the L64002 device when the L64007 detects
an attempt by the host processor to access the L64002 (CS = LOW) in
address space 0xFFFF8 - 0xFFFFF. If the internal arbitration logic grants
the access, the AV_CS signal is asserted to the L64002.
The following table shows the register mapping of the L64002 registers
address space. Only the lower 8 bits of each register are valid.
Table 4.1
Address Space of
L64002 Registers
15
0
FSC Clock Divide Value Register
Word Address
Access
L64002 Group
0xFFFF8
R/W
0
0xFFFF9
R/W
1
0xFFFFA
R/W
2
0xFFFFB
R/W
3
0xFFFFC
R/W
4
0xFFFFD
R/W
5
0xFFFFE
R/W
6
0xFFFFF
R/W
7