register
12 Wed May 28 17:37:25 1997
Draft 1/21/97
4-12
Registers
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
4.4
Video PID
Control
Registers
(Group 2)
(Group 1).” This group of registers controls the processing of the video
PES stream of the program to be decoded. The group includes registers
to control the PID processing, as well as a group of registers to control
the store of audio PES data in the memory for extended channel mode
operation.
The Video PID Control Registers occupy memory space from 0xFFDF0
to 0xFFDFF.
The L64007 assumes that the payload data for this PID is a video PES
stream. The data coming on this PID is transferred to the on-chip video
transport buffer and to the A/V decoder output.
4.4.1
Video PID Value
(VPID)
The VPID is a 13-bit register comprising the Video PID eld used in the
PID detection process for the video stream of the program being
decoded. When a transport packet comes into the L64007 containing a
PID value matching the specied VPID, the transport payload is pro-
cessed as a video PES stream of the program being decoded. The ACT
bit in the Video PID Control Register must be set to 1 for this register to
become active.
The VPID Register bit eld is described below.
RES
Reserved
[15:13]
These bits are reserved.
VPID
Video PID
[12:0]
This 13-bit eld determines the value to be compared
with the PID eld transmitted in the transport packet
header. If the PID value matches the VPID value, and the
ACT bit is set to 1, the PPU continues to parse the data
in this transport packet. The payload in this transport
packet is considered to be video PES data. The common
use of the PID eld in MPEG-2 compliant system is
shown below (example only). The user can program any
value into the application. Only the null PID, 0x1FFF,
causes the L64007 to discard a null packet.
15
13
12
0
RES
VPID