- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384544 > ISPMACH4ACPLDFAMILY (Lattice Semiconductor Corporation) High Performance E 2 CMOS In-System Programmable Logic PDF資料下載
參數(shù)資料
| 型號： | ISPMACH4ACPLDFAMILY |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | 高的E 2的CMOS在系統(tǒng)可編程邏輯 |
| 文件頁數(shù)： | 9/62頁 |
| 文件大小： | 1180K |
| 代理商： | ISPMACH4ACPLDFAMILY |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
ispMACH 4A Family
9
Note that the configuration of the logic allocator has absolutely no impact on the speed of the
signal. All configurations have the same delay. This means that designers do not have to decide
between optimizing resources or speed; both can be optimized.
If not used in the cluster, the extra product term can act in conjunction with the basic cluster to
provide XOR logic for such functions as data comparison, or it can work with the D-,T-type flip-
flop to provide for J-K, and S-R register operation. In addition, if the basic cluster is routed to
another macrocell, the extra product term is still available for logic. In this case, the first XOR
input will be a logic 0. This circuit has the flexibility to route product terms elsewhere without
giving up the use of the macrocell.
Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the
ends of the block have fewer product terms available.
0
17466G-007
Figure 3. Logic Allocator Configurations: Synchronous Mode
a. Basic cluster with XOR
b. Extended cluster, active high
c. Extended cluster, active low
d. Basic cluster routed away;
single-product-term, active high
e. Extended cluster routed away
0
17466G-008
Figure 4. Logic Allocator Configurations: Asynchronous Mode
b. Extended cluster, active high
c. Extended cluster, active low
e. Extended cluster routed away
d. Basic cluster routed away;
single-product-term, active high
a. Basic cluster with XOR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5520V-01TN100C | Linear Array Light; LED Color:Green; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:530nm |
| ISPPAC-CLK55xx | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48C | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48I | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPNANO S3 KIT | 功能描述:ISP PORTABLE PROGRAMMER RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 內(nèi)電路編程器、仿真器以及調(diào)試器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 19/Jul/2010 標準包裝:1 系列:* 類型:* 適用于相關(guān)產(chǎn)品:* 所含物品:* |
| ISPNANO UPG17 | 功能描述:ISP NANO DEVICE LIB UPGRAGE RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 知識產(chǎn)權(quán) (IP) 系列:* 標準包裝:1 系列:Nios®II 類型:Nios II 功能:C 到硬件編譯器 許可證:初始許可證 |
| ISPNANO-UPG10AR | 功能描述:ISP NANO RUN TIME LICENSE RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 知識產(chǎn)權(quán) (IP) 系列:* 標準包裝:1 系列:Nios®II 類型:Nios II 功能:C 到硬件編譯器 許可證:初始許可證 |
| ISPNANO-UPG18 | 功能描述:ISP PORTABLE PROGRAMMER USB RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 軟件 系列:* 標準包裝:1 系列:ISE® 設(shè)計套件 類型:訂閱 適用于相關(guān)產(chǎn)品:Xilinx FPGAs 其它名稱:Q4986209T1081384 |
| ISPNANO-UPG7 | 功能描述:JTAG ISP UPGRADE FOR ATMEL AVR RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 知識產(chǎn)權(quán) (IP) 系列:* 標準包裝:1 系列:Nios®II 類型:Nios II 功能:C 到硬件編譯器 許可證:初始許可證 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。