參數(shù)資料
型號(hào): ISPMACH4ACPLDFAMILY
廠商: Lattice Semiconductor Corporation
英文描述: High Performance E 2 CMOS In-System Programmable Logic
中文描述: 高的E 2的CMOS在系統(tǒng)可編程邏輯
文件頁(yè)數(shù): 39/62頁(yè)
文件大小: 1180K
代理商: ISPMACH4ACPLDFAMILY
ispMACH 4A Family
39
Input Register Delays with ZHT Option:
t
SIRZ
t
HIRZ
Input register hold time - ZHT
Input Latch Delays with ZHT Option:
Input register setup time - ZHT
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
ns
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
t
SILZ
t
HILZ
t
PDIL
Zi
Output Delays:
Input latch setup time - ZHT
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
ns
Input latch hold time - ZHT
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
Transparent input latch to internal
feedback - ZHT
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
ns
t
BUF
t
SLW
t
EA
t
ER
Power Delay:
Output buffer delay
1.5
1.5
1.8
2.0
2.5
3.0
3.0
3.0
ns
Slowslewrate delay adder
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
Output enable time
7.5
7.5
8.5
8.5
9.5
10.0
12.0
15.0
ns
Output disable time
7.5
7.5
8.5
8.5
9.5
10.0
12.0
15.0
ns
t
PL
Reset and Preset Delays:
Power-down mode delay adder
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
t
SRi
Asynchronous reset or preset to internal
register output
7.5
7.7
8.0
8.0
9.5
11.0
13.0
16.0
ns
t
SR
Asynchronous reset or preset to register
output
9.0
9.2
10.0
10.0
12.0
14.0
16.0
19.0
ns
t
SRR
Asynchronous reset and preset register
recovery time
7.0
7.0
7.5
7.5
8.0
8.0
10.0
15.0
ns
t
SRW
Clock/LE Width:
Asynchronous reset or preset wdth
7.0
7.0
8.0
8.0
10.0
10.0
12.0
15.0
ns
t
WLS
t
WHS
t
WLA
t
WHA
Gobal clock wdth low
2.0
2.0
2.5
2.5
3.0
4.0
5.0
6.0
ns
Gobal clock wdth high
2.0
2.0
2.5
2.5
3.0
4.0
5.0
6.0
ns
Product termclock wdth low
3.0
3.0
3.5
3.5
4.0
5.0
8.0
9.0
ns
Product termclock wdth high
3.0
3.0
3.5
3.5
4.0
5.0
8.0
9.0
ns
t
GWS
Gobal gate wdth low(for low
transparent) or high (for high
transparent)
4.0
4.0
4.5
4.5
5.0
5.0
6.0
6.0
ns
t
GWA
Product termgate wdth low(for low
transparent) or high (for high
transparent)
4.0
4.0
4.5
4.5
5.0
5.0
6.0
9.0
ns
t
WIRL
Input register clock wdth low
t
WIRH
Input register clock wdth high
t
WIL
Input latch gate wdth
3.0
3.0
3.5
3.5
4.0
5.0
6.0
6.0
ns
3.0
3.0
3.5
3.5
4.0
5.0
6.0
6.0
ns
4.0
4.0
4.5
4.5
5.0
5.0
6.0
6.0
ns
ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES
1
(CONTINUED)
-5
-55
-6
-65
-7
-10
-12
-14
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
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