參數(shù)資料
型號: ISPMACH4ACPLDFAMILY
廠商: Lattice Semiconductor Corporation
英文描述: High Performance E 2 CMOS In-System Programmable Logic
中文描述: 高的E 2的CMOS在系統(tǒng)可編程邏輯
文件頁數(shù): 1/62頁
文件大?。?/td> 1180K
代理商: ISPMACH4ACPLDFAMILY
Publication#
ISPM4A
Amendment/
0
Rev:
D
Issue Date:
August 2000
ispMACH
4A CPLD Family
High Performance E
2
CMOS
In-System Programmable Logic
FEATURES
N
High-performance, E
2
CMOS 3.3-V & 5-V CPLD families
N
Flexible architecture for rapid logic designs
— Excellent First-Time-Fit
TM
and refit feature
— SpeedLocking
TM
performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
N
High speed
— 5.0ns t
PD
Commercial and 7.5ns t
PD
Industrial
— 182MHz f
CNT
N
32 to 512 macrocells; 32 to 768 registers
N
44 to 388 pins in PLCC, PQFP TQFP BGA, fpBGA and caBGA packages
N
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
N
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-Friendly
inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
N
Advanced E
CMOS process provides high-performance, cost-effective solutions
N
Supported by ispDesignEXPERT
software for rapid logic development
— Supports HDL design methodologies with results optimized for ispMACH 4A
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
N
Lattice and third-party hardware programming support
— LatticePRO
software for in-system programmability support on PCs and automated test
equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
TM
2
TM
TM
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