參數(shù)資料
型號: ISP1161A1
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus single-chip host and device controller
中文描述: 通用串行總線的單芯片主機(jī)和設(shè)備控制器
文件頁數(shù): 82/127頁
文件大?。?/td> 2762K
代理商: ISP1161A1
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
82 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
Code (Hex): A8 —
write
13.5.3
HcSoftwareReset Register
This is a soft reset command. The microprocessor writes A9H to ISP1161’s
command port, resetting all the HC’s internal registers except for the internal FIFO
buffer RAM.
Code (Hex): A9 —
write
13.6 HC buffer RAM control registers
13.6.1
HcITLBufferLength Register
Write to this register to assign the ITL buffer size in bytes for both ITL0 and ITL1
simultaneously. Thus, the ITL0 and ITL1 always have the same size.
Must follow the formula:
ATL buffer length + 2
×
(ITL buffer size)
1000H (that is, 4 kbytes)
where: ITL buffer size = ITL0 buffer length = ITL1 buffer length
Table 58: HcSoftwareReset Register: bit allocation
Bit
15
Symbol
Reset
X
Access
Bit
7
Symbol
Reset
1
Access
14
13
12
11
10
9
8
Reset[15:8]
X
X
X
X
X
X
X
W
6
5
4
3
2
1
0
Reset[7:0]
1
1
1
0
1
1
0
W
Table 59: HcSoftwareReset Register: bit description
Bit
Symbol
Description
15 to 0
Reset[15:0] Soft reset command
Table 60: HcITLBufferLength Register: bit allocation
Bit
15
Symbol
Reset
0
Access
Bit
7
Symbol
Reset
0
Access
14
13
12
11
10
9
8
ITLBufferLength[15:8]
0
R/W
4
ITLBufferLength[7:0]
0
R/W
0
0
0
0
0
0
6
5
3
2
1
0
0
0
0
0
0
0
相關(guān)PDF資料
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ISP1161A1BD Universal Serial Bus single-chip host and device controller
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