參數(shù)資料
型號: ISP1161A1
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus single-chip host and device controller
中文描述: 通用串行總線的單芯片主機和設備控制器
文件頁數(shù): 49/127頁
文件大?。?/td> 2762K
代理商: ISP1161A1
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
49 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
12.2 8237 compatible mode
The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware
Configuration Register (see
Table 81
). The pin functions for this mode are shown in
Table 11
.
The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA
controller. It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA
controller, but it is transferred between an I/O port and a memory address. A typical
example of ISP1161 DC in 8237 compatible DMA mode is given in
Figure 38
.
The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request), HLDA
(Hold Acknowledge) and EOP (End-Of-Process). The bus operation is controlled via
MEMR (Memory Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).
11
12
13
14
1100
1101
1110
1111
OUT: read
OUT: read
OUT: read
OUT: read
IN: write
IN: write
IN: write
IN: write
Table 10: Endpoint selection for DMA transfer
…continued
Endpoint
identifier
EPIDX[3:0]
Transfer direction
EPDIR = 0
EPDIR = 1
Table 11: 8237 compatible mode: pin functions
Symbol
Description
DREQ2
DC’s DMA request
DACK2
DC’s DMA
acknowledge
EOT
end of transfer
RD
read strobe
I/O
O
I
Function
ISP1161 DC requests a DMA transfer
DMA controller confirms the transfer
I
I
DMA controller terminates the transfer
instructs ISP1161 DC to put data on the
bus
instructs ISP1161 DC to get data from the
bus
WR
write strobe
I
Fig 38. ISP1161’s device controller in 8237 compatible DMA mode.
D0 to D15
CPU
004aaa009
RAM
ISP1161
DEVICE
CONTROLLER
DMA
CONTROLLER
8237
DREQ
DREQ2
DACK2
HRQ
HLDA
HRQ
HLDA
DACK
IOR
IOW
MEMR
MEMW
RD
WR
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